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參數(shù)資料
| 型號： | MAX1332 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 3Msps/2Msps, 5V/3V, 2-Channel, True-Differential 12-Bit ADCs |
| 中文描述： | 3Msps/2Msps，5V/3V，雙通道，真差分12位ADC |
| 文件頁數(shù)： | 13/25頁 |
| 文件大小： | 379K |
| 代理商： | MAX1332 |
Detailed Description
The MAX1332/MAX1333 use an input track and hold
(T/H) circuit along with a successive-approximation
register (SAR) to convert a differential analog input sig-
nal to a digital 12-bit output. The serial interface
requires only three digital lines (SCLK, CNVST, and
DOUT) and provides easy interfacing to microcon-
trollers (μCs) and DSPs.
Figure 2 shows the simplified
block diagram for the MAX1332/MAX1333.
Power Supplies
The MAX1332/MAX1333 accept two power supplies
that allow the digital noise to be isolated from sensitive
analog circuitry. For both the MAX1332 and MAX1333,
the digital power-supply input accepts a supply voltage
of +2.7V to +3.6V. However, the supply voltage range
for the analog power supply is different for each
device. The MAX1332 accepts a +4.75V to +5.25V
analog power supply, and the MAX1333 accepts
a +2.7V to +3.6V analog power supply. See the
Layout,
Grounding, and Bypassing
section for information on
how to isolate digital noise from the analog power input.
The MAX1332/MAX1333s’ analog power supply con-
sists of one AV
DD
input, two AGND inputs, and the
exposed paddle (EP). The digital power input consists
of one DV
DD
input and one DGND input. Ensure that
the potential on both AGND inputs is the same.
Furthermore, ensure that the potential between AGND
and DGND is limited to ±0.3V. Ideally there should be
no potential difference between AGND and DGND.
There are no power sequencing issues between AV
DD
and DV
DD
. The analog and digital power supplies are
insensitive to power-up sequencing.
True-Differential Analog Input T/H
The equivalent input circuit of Figure 3 shows the
MAX1332/MAX1333s’ input architecture, which is com-
posed of a T/H, a comparator, and a switched-capaci-
tor DAC. On power-up, the MAX1332/MAX1333 enter
full power-down mode. Drive CNVST high to exit full
power-down mode and to start acquiring the input. The
positive input capacitor is connected to AIN_P and the
negative input capacitor is connected to AIN_N. The
T/H enters its hold mode on the falling edge of CNVST
and the ADC starts converting the sampled difference
between the analog inputs. Once a conversion has
been initiated, the T/H enters acquisition mode for the
next conversion on the 13th falling edge of SCLK after
CNVST has been transitioned from high to low.
The time required for the T/H to acquire an input signal
is determined by how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens. The acquisition time,
t
ACQ
, is the minimum time needed for the signal to be
acquired. It is calculated by the following equation:
t
ACQ
≥
k x (R
SOURCE
+ R
IN
) x C
IN
where:
The constant k is the number of RC time constants
required so that the voltage on the internal sampling
capacitor reaches N-bit accuracy, i.e., so that the dif-
ference between the input voltage and the sampling
capacitor voltage is equal to 0.5 LSB. N = 12 for the
MAX1332/MAX1333.
R
IN
= 250
is the equivalent differential analog input
resistance, C
IN
= 14pF is the equivalent differential ana-
log input capacitance, and R
SOURCE
is the source
impedance of the input signal. Note that t
ACQ
is never
less than 52μs for the MAX1332 and 78μs for the
MAX1333, and any source impedance below 160
does
not significantly affect the ADC’s AC performance.
Input Bandwidth
The ADC’s input-tracking circuitry has a 5MHz small-
signal bandwidth, making it possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
k
N
=
≈
9
2 2
ln(
)
M
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
______________________________________________________________________________________
13
DOUT
DV
DD
REF
12-BIT SAR
ADC
CNVST
SCLK
SHDN
CHSEL
BIP/UNI
DGND
CONTROL
LOGIC AND
TIMING
AV
DD
AGND
AIN0P
AIN0N
INPUT
MUX
AND T/H
AIN1P
AIN1N
MAX1332
MAX1333
OUTPUT
BUFFER
Figure 2. Simplified Functional Diagram
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| MAX13325EVKIT+ | 功能描述:緩沖器和線路驅(qū)動器 MAX13325 EVKIT RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| MAX13325GUI/V+ | 功能描述:緩沖器和線路驅(qū)動器 Dual Audio Line Driver RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| MAX13325GUI/V+T | 功能描述:緩沖器和線路驅(qū)動器 Dual Audio Line Driver RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| MAX13326GUI/V+ | 功能描述:緩沖器和線路驅(qū)動器 Dual Audio Line Driver RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
| MAX13326GUI/V+T | 功能描述:緩沖器和線路驅(qū)動器 Dual Audio Line Driver RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel |
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