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參數(shù)資料
| 型號： | MAX132MRG |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 【18-Bit ADC with Serial Interface |
| 中文描述： | 1-CH 18-BIT MULTI-SLOPE ADC, SERIAL ACCESS, CDIP24 |
| 封裝： | CERDIP-24 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 129K |
| 代理商： | MAX132MRG |
M
±18-Bit ADC with S erial Interfac e
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(V+ = 5V, V- = -5V, DGND = AGND = IN LO = REF- = 0V, REF+ = 545mV, R
INT
= 602k
, C
INT
= 0.0047μF, C
REF
= 0.1μF,
f
CLK
= 32,768Hz, 60Hz mode, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
INTERFACE TIMING
(Test Circuit of Figure 1, Figure 2, V+ = 5V, V- = -5V, DGND = AGND = 0V, T
A
= +25°C, unless otherwise noted.) (Note 3)
Note 1:
±18-bit accuracy achieved by averaging multiple conversions.
Note 2:
Maximum deviation from best straight-line fit.
Note 3:
Guaranteed by design, not tested.
Note 4:
Difference in reading for equal positive and negative inputs near full scale.
DOUT, I
OUT
= -100μA
EOC, P0–P3, I
OUT
= -100μA
DOUT, I
OUT
= 1.6mA
EOC, P0–P3, I
OUT
= 100μA
Referred to DGND, 4.5V
≤
V+
≤
5.5V, CS, DIN, SCLK
DOUT, I
OUT
= -1mA
CS, DIN, SCLK, and DOUT when three-stated
CS, DIN, SCLK, and DOUT when three-stated
Referred to DGND, 4.5V
≤
V+
≤
5.5V, CS, DIN, SCLK
CONDITIONS
4.0
4.0
4.5
4.7
0.1
0.1
3.5
4.3
pF
5
C
IN
Input Capacitance
nA
±10
±500
I
IN
Input Current
V
0.8
V
IL
Input Low
V
V
OH
Output High
0.4
0.4
V
V
OL
Output Low
V
2.4
V
IH
Input High
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
DIGITAL SECTION
CONDITIONS
ns
ns
500
400
t
1
t
2
CS Lead Time
CS Lag Time
μs
ns
ns
1
0
t
5
t
6
t
7
CS High Pulse Width
DIN to SCLK Setup Time
DIN to SCLK Hold Time
ns
300
t
4
S
CLK
Low Time
ns
400
t
3
S
CLK
High Time
UNITS
MIN
TYP
MAX
SYMBOL
PARAMETER
See Figure 4
See Figure 3
ns
ns
320
350
t
10
t
11
DOUT Disable Time to Three-State
Delay to P0–P3 High
ns
60
t
9
Data Valid
ns
320
t
8
DOUT Access Time from Three-State
200
ns
230
350
t
12
Delay to P0–P3 Low
230
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