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參數(shù)資料
| 型號： | MAX1303BEUP+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 20/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT MULT RANGE 20TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS |
| 標(biāo)準(zhǔn)包裝： | 74 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 115k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 879mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極；2 個差分，雙極 |
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MAX1303
4-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
______________________________________________________________________________________
27
Gain Error
When a positive full-scale voltage is applied to the con-
verter inputs, the digital output is all ones (0xFFFF). The
transition from 0xFFFE to 0xFFFF occurs at 1.5 LSB
below full scale. Gain error is the amount of deviation
between the measured full-scale transition point and
the ideal full-scale transition point with the offset error
removed and all untested channels grounded.
Unipolar Endpoint Overlap
Unipolar endpoint overlap is the change in offset when
switching between complementary input voltage
ranges. For example, the difference between the volt-
age that results in a 0xFFFF output in the -VREF/2 to 0V
input voltage range and the voltage that results in a
0x0000 output in the 0V to +VREF/2 input voltage range
is the unipolar endpoint overlap. The unipolar endpoint
overlap is positive for the MAX1303, preventing loss of
signal or a dead zone when switching between adja-
cent analog input voltage ranges.
Small-Signal Bandwidth
A 100mVP-P sine wave is applied to the ADC, and the
input frequency is then swept up to the point where the
amplitude of the digitized conversion result has
decreased by -3dB.
Full-Power Bandwidth
A 95% of full-scale sine wave is applied to the ADC,
and the input frequency is then swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB.
Common-Mode Rejection Ratio (CMRR)
CMRR is the ability of a device to reject a signal that is
“common” to or applied to both input terminals. The
common-mode signal can be either an AC or a DC sig-
nal or a combination of the two. CMR is expressed in
decibels. Common-mode rejection ratio is the ratio of
the differential signal gain to the common-mode signal
gain. CMRR applies only to differential operation.
Power-Supply Rejection Ratio (PSRR)
PSRR is the ratio of the output-voltage shift to the
power-supply-voltage shift for a fixed input voltage. For
the MAX1303, AVDD1 can vary from 4.75V to 5.25V.
PSRR is expressed in decibels and is calculated using
the following equation:
For the MAX1303, PSRR is tested in bipolar operation
with the analog inputs grounded.
Aperture Jitter
Aperture jitter, tAJ, is the statistical distribution of the
variation in the sampling instant (Figure 19).
Aperture Delay
Aperture delay, tAD, is the time from the falling edge of
SCLK to the sampling instant (Figure 19).
Signal-to-Noise Ratio (SNR)
SNR is computed by taking the ratio of the RMS signal
to the RMS noise. RMS noise includes all spectral com-
ponents to the Nyquist frequency excluding the funda-
mental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise plus distortion. RMS noise plus
distortion includes all spectral components to the
Nyquist frequency excluding the fundamental and the
DC offset.
Effective Number of Bits (ENOB)
ENOB indicates the global accuracy of an ADC at a
specific input frequency and sampling rate. With an
input range equal to the ADC’s full-scale range, calcu-
late the ENOB as follows:
ENOB
SINAD
.
=
176
602
SINAD dB
Signal
Noise
RMS
(
)
log
=×
20
PSRR dB
VV
OUT
[
]
log
.
(.
)
(.
)
=×
20
525
4 75
525
4 75
tAD
tAJ
INTCLK
(MODE 2)
ANALOG INPUT
TRACK AND HOLD
TRACK
HOLD
SAMPLE INSTANT
SCLK
(MODE 0)
13
14
15
SCLK
(MODE 1)
15
16
10
11
12
Figure 19. Aperture Diagram
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參數(shù)描述 |
|---|---|
| MAX1303BEUP+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 4Ch 115ksps 4.136V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1303BEUP+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 4Ch 115ksps 4.136V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1303BEUP-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX13041ASD/V+ | 功能描述:CAN 接口集成電路 80V Fault-Protected High-Speed RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
| MAX13041ASD/V+T | 功能描述:CAN 接口集成電路 80V Fault-Protected High-Speed RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
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