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參數(shù)資料
| 型號： | MAX1285BESA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 300KSPS 8-SOIC |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 300k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
______________________________________________________________________________________
13
Figure 14 shows the recommended system ground con-
nections. Establish a single-point analog ground (“star”
ground point) at GND, separate from the logic ground.
Connect all other analog grounds and DGND to this star
ground point for further noise reduction. No other digital
system ground should be connected to this single-point
analog ground. The ground return to the power supply for
this ground should be low impedance and as short as
possible for noise-free operation.
High-frequency noise in the VDD power supply may affect
the ADC’s high-speed comparator. Bypass this supply to
the single-point analog ground with 0.1F and 10F
bypass capacitors. Minimize capacitor lead lengths for
best supply noise rejection. To reduce the effects of sup-
ply noise, a 10
Ω resistor can be connected as a lowpass
filter to attenuate supply noise (Figure 14).
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function,
once offset and gain errors have been nullified. The static
linearity parameters for the MAX1284/MAX1285 are mea-
sured using the endpoints method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A DNL
error specification of 1LSB or less guarantees no missing
codes and a monotonic transfer function.
CS
SCLK
DOUT
916
8
1
D0
D11
D10
D9
D8
D6
D5
D4
D3
D2
D1
D7
FIRST BYTE READ
SECOND BYTE READ
HIGH-Z
SCLK
DOUT
CS
14
13
D11
D10
D9
D8
D4
D5
D6
D3
D2
D1
D0
HIGH-Z
D7
HIGH-Z
Figure 12. SPI/MICROWIRE Serial Interface Timing (CPOL = CPHA = 0)
Figure 13. QSPI Serial Interface Timing (CPOL = 0, CPHA = 1)
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相關代理商/技術參數(shù) |
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| MAX1286ETA+ | 制造商:Maxim Integrated Products 功能描述: 制造商:Maxim Integrated Products 功能描述:ADC SGL SAR 150KSPS 12-BIT SERL 8TDFN EP - Rail/Tube |
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