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參數(shù)資料
| 型號： | MAX1285BESA+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 300KSPS 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 300k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
MAX1284/MAX1285
400ksps/300ksps, Single-Supply, Low-Power,
Serial 12-Bit ADCs with Internal Reference
10
______________________________________________________________________________________
Figure 5. Supply Current vs. Conversion Rate
To start a conversion, pull CS low. At CS’s falling edge,
the T/H enters its hold mode and a conversion is initiat-
ed. Data can then be shifted out serially with the exter-
nal clock.
Using SHDN to Reduce Supply Current
Power consumption can be reduced significantly by
shutting down the MAX1284/MAX1285 between con-
versions. Figure 5 shows a plot of average supply cur-
rent versus conversion rate. The wake-up time (tWAKE)
is the time from when SHDN is deasserted to the time
when a conversion may be initiated (Figure 6). This
time depends on the time in shutdown (Figure 7)
because the external 4.7F reference bypass capacitor
loses charge slowly during shutdown and can be as
long as 2ms.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CS and SCLK digital inputs. The timing dia-
grams of Figures 8 and 9 outline serial-interface
operation.
A CS falling edge initiates a conversion sequence: the
T/H stage holds the input voltage, the ADC begins to
convert, and DOUT changes from high impedance to
logic low. SCLK is used to drive the conversion
process, and it shifts data out as each bit of conversion
is determined.
SCLK begins shifting out the data after the rising edge
of the third SCLK pulse. DOUT transitions 20ns after
each SCLK rising edge. The third rising clock edge
produces the MSB of the conversion at DOUT, followed
by the remaining bits. Since there are twelve data bits
and three leading zeros, at least fifteen rising clock
edges are needed to shift out these bits. Extra clock
pulses occurring after the conversion result has been
clocked out, and prior to a rising edge of CS, produce
trailing zeros at DOUT and have no effect on converter
operation.
Pull CS high after reading the conversion’s LSB. For
maximum throughout, CS can be pulled low again to
initiate the next conversion immediately after the speci-
fied minimum time (tCS).
Output Coding and Transfer Function
The data output from the MAX1284/MAX1285 is binary,
and Figure 10 depicts the nominal transfer function.
Code transitions occur halfway between successive-
integer LSB value VREF = +2.5V, and 1LSB = 610V or
2.5V/4096.
COMPLETE CONVERSION SEQUENCE
CONVERSION 0
CONVERSION 1
POWERED-UP
POWERED-DOWN
tWAKE
DOUT
CS
SHDN
Figure 6. Shutdown Sequence
0.1
1
100
10
1k
10k
0.1
10
1
100
1000 10,000 100,000
CONVERSION RATE (ksps)
SUPPLY
CURRENT
(μ
A)
VDD = 3V
DOUT = FS
RL =
∞
CL = 10pF
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