參數(shù)資料
型號: MAX1186ECM+TD
廠商: Maxim Integrated Products
文件頁數(shù): 6/21頁
文件大?。?/td> 0K
描述: IC ADC 10BIT 40MSPS DL 48-TQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,000
位數(shù): 10
采樣率(每秒): 40M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 150mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤
供應商設備封裝: 48-TQFP 裸露焊盤(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個單端,雙極;2 個差分,雙極
MAX1186
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Multiplexed Parallel Outputs
14
______________________________________________________________________________________
Applications Information
Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a VDD / 2 output voltage for level
shifting purposes. The input is buffered and then split to
a voltage follower and inverter. One lowpass filter per
ADC suppresses some of the wideband noise associat-
ed with high-speed operational amplifiers that follows
the amplifiers. The user may select the RISO and CIN
values to optimize the filter performance, to suit a par-
ticular application. For the application in Figure 5, a
RISO of 50
is placed before the capacitive load to pre-
vent ringing and oscillation. The 22pF CIN capacitor
acts as a small bypassing capacitor.
Using Transformer Coupling
An RF transformer (Figure 6) provides an excellent
solution to convert a single-ended source signal to a
fully differential signal, required by the MAX1186 for
optimum performance. Connecting the center tap of the
transformer to COM provides a VDD / 2 DC level shift to
the input. Although a 1:1 transformer is shown, a step-
up transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the over-
all distortion.
In general, the MAX1186 provides better SFDR and
THD with fully differential input signals than single-
ended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower as both inputs (INA+, INA- and/or INB+, INB-) are
balanced, and each of the ADC inputs only requires
half the signal swing compared to single-ended mode.
tDOB
tCL
tCH
tCLK
tDOA
tDA/B
5 CLOCK-CYCLE LATENCY (CHA), 5.5 CLOCK-CYCLE LATENCY (CHB)
A/B
CHB
D0A/B–D9A/B
D0B
CHA
D1A
CHB
D1B
CHA
D2A
CHB
D2B
CHA
D3A
CHB
D3B
CHA
D4A
CHB
D4B
CHA
D5A
CHB
D5B
CHA
D6A
CHB
D6B
CHA
CHB
CLK
OUTPUT
D0A/B–D9A/B
OE
tDISABLE
tENABLE
HIGH
IMPEDANCE
HIGH
IMPEDANCE
VALID DATA
Figure 3. Timing Diagram for Multiplexed Outputs
Figure 4. Output Timing Diagram
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