參數(shù)資料
型號(hào): MAX11060GUU+
廠(chǎng)商: Maxim Integrated Products
文件頁(yè)數(shù): 2/35頁(yè)
文件大?。?/td> 0K
描述: IC ADC 16BIT DELTA SIGMA 38TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
位數(shù): 16
采樣率(每秒): 3.07M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 4
功率耗散(最大): 1.1W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 106°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 38-TFSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 38-TSSOP
包裝: 管件
輸入數(shù)目和類(lèi)型: 8 個(gè)單端,雙極;4 個(gè)差分,雙極
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
10
Maxim Integrated
Pin Description (continued)
PIN
NAME
FUNCTION
11, 28
DGND
Digital Ground
12, 27
DVDD
Positive Digital Supply Voltage. Bypass each DVDD to DGND with a 1μF capacitor in parallel with a
0.01μF capacitor as close as possible to the device.
13
CASCIN
Cascade Input. A logic-low on CASCIN while CS is a logic-low during the last cycle of a byte signals the
device to perform the requested data transfer during subsequent bytes using DIN and DOUT. Once the
requested transfer is completed, the part three-states DOUT and ignores DIN until a new command is
issued. CASCIN is clocked in at the rising edge of SCLK. Connect CASCIN to DGND when not daisy
chaining multiple devices. See the Multiple Device Connection section for connection recommendations.
14
CASCOUT
Cascade Output. CASCOUT is driven low during the last cycle of the last byte of a data transfer to signal
the next device in the daisy-chain to begin transferring data on the next byte. CASCOUT changes after
the rising edge of SCLK. Leave CASCOUT unconnected when not daisy chaining multiple devices. See
the Multiple Device Connection section.
15
CS
Active-Low Chip-Select Input. A falling edge on CS while CASCIN is a logic-low enables DIN and DOUT
for data transfer. A logic-high on CS prevents data from being clocked in on DIN and places DOUT in a
high-impedance state.
16
SCLK
Serial-Clock Input. Clocks in data at DIN on the falling edge of SCLK and clocks out data at DOUT on the
rising edge of SCLK. SCLK must idle high (CPOL = 1).
17
DIN
Serial Data Input. Data at DIN is clocked in on the falling edge of SCLK.
18
DOUT
Serial Data Output. The drive for DOUT is enabled by a falling edge on CS while CASCIN is low or by a
falling edge on CASCIN while CS is low. DOUT is disabled/three-stated when CS is high or after the
appropriate number of data bytes have been transferred in response to the requested command. Data is
clocked out at DOUT on the rising edge of SCLK.
19
FAULT
Active-Low Overvoltage Fault Indicator Output. FAULT goes low when any analog input goes outside the fault
threshold range (between VPFT and VNFT). The FAULT output is open drain with a 30k
Ω internal pullup
resistor, allowing wire-NOR functionality. See the Analog Input Overvoltage and Fault Protection section.
20
OVRFLW
Active-Low Channel Data Overflow Output. OVRFLW goes low when a conversion result goes outside the
voltage range bounded by the positive and negative full scale on one or more of the analog input
channels or when FAULT goes low. The OVRFLW output is open drain with a 30k
Ω internal pullup resistor,
allowing wire-NOR functionality. See the Analog Input Overvoltage and Fault Protection section.
21
CLKOUT
Buffered Clock Output. When the XTALEN bit in the configuration register is 1 and a crystal is installed
between XIN and XOUT, CLKOUT provides a buffered version of the internal oscillator’s clock. Setting the
XTALEN bit to 0 places CLKOUT in a high-impedance state.
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