參數(shù)資料
型號(hào): MAX11060GUU+
廠商: Maxim Integrated Products
文件頁數(shù): 1/35頁
文件大小: 0K
描述: IC ADC 16BIT DELTA SIGMA 38TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
位數(shù): 16
采樣率(每秒): 3.07M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 4
功率耗散(最大): 1.1W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 106°C
安裝類型: 表面貼裝
封裝/外殼: 38-TFSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 38-TSSOP
包裝: 管件
輸入數(shù)目和類型: 8 個(gè)單端,雙極;4 個(gè)差分,雙極
19-5741; Rev 3; 8/12
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
MAX11040K/MAX11060
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
EVALUATION KIT AVAILABLE
General Description
The MAX11040K/MAX11060 are 24-/16-bit, 4-channel,
simultaneous-sampling, sigma-delta analog-to-digital
converters (ADCs). The devices allow simultaneous
sampling of as many as 32 channels using a built-in
cascade feature to synchronize as many as eight
devices. The serial interface of the devices allows read-
ing data from all the cascaded devices using a single
command. Four modulators simultaneously convert
each fully differential analog input with a programmable
data output rate ranging from 0.25ksps to 64ksps. The
devices achieve 106dB SNR at 16ksps and 117dB SNR
at 1ksps (MAX11040K). The devices operate from a
single +3V supply. The differential analog input range is
±2.2V when using the internal reference; an external
reference is optional. Each input is overvoltage protect-
ed up to ±6V without damage. The devices use an
internal crystal oscillator or an external source for clock.
The devices are compatible with SPI, QSPI,
MICROWIRE, and DSP-compatible 4-wire serial inter-
faces. An on-board interface logic allows one serial inter-
face (with a single chip select) to control up to eight
cascaded devices or 32 simultaneous sampling analog
input channels.
The devices are ideally suited for power-management
systems. Each channel includes an adjustable sam-
pling phase enabling internal compensation for phase
shift due to external dividers, transformers, or filters at
the inputs. The output data rate is adjustable with a
0.065% resolution (at 16ksps or below) to track the
varying frequency of a periodic input. A SYNC input
allows periodic alignment of the conversion timing of
multiple devices with a remote timing source.
The devices are available in a 38-pin TSSOP package speci-
fied over the -40°C to +105°C industrial temperature range.
Applications
Power-Protection Relay Equipment
Multiphase Power Systems
Industrial Data-Acquisition Systems
Medical Instrumentation
Features
o Four Fully Differential Simultaneously Sampled
Channels
o Cascadable for Up to 32 Channels of
Simultaneous Sampling
o 106dB (MAX11040K) SNR at 16ksps
o 117dB (MAX11040K) SNR at 1ksps
o 0.25% Error Over a 1000:1 Dynamic Range,
Processed Over 16.7ms (MAX11040K)
o ±2.2V Full-Scale Input Range
o ±6V Overvoltage Protected Inputs
o Internal Crystal Oscillator
o 2.5V, 50ppm/°C Internal Reference or External
Reference
o Programmable Output Data Rate
0.25ksps to 64ksps Range
0.065% Resolution
o Programmable Sampling Phase
0 to 333s Delay in 1.33s Steps
o SPI-/QSPI-/MICROWIRE-/DSP-Compatible 4-Wire
Serial Interface
o Cascadable Interface Allows Control of Up to
Eight Devices with a Single
CS Signal
o 3.0V to 3.6V Analog Supply Voltage
o 2.7V to VAVDD Digital Supply Voltage
o 38-Pin TSSOP Package
Ordering Information
+
Denotes a lead(Pb)-free/RoHS-compliant package.
PART
TEMP RANGE
PIN-PACKAGE
MAX11040KGUU+
-40°C to +105°C
38 TSSOP
MAX11060GUU+
-40°C to +105°C
38 TSSOP
MICROWIRE is a registered trademark of National Semiconductor Corp.
QSPI is a trademark of Motorola, Inc.
MAX11040K
24-BIT
ADC
DIGITAL
FILTER
2.5V
REFERENCE
CRYSTAL
OSCILLATOR
REFIO
AIN3+
AIN3-
REF3
24-BIT
ADC
DIGITAL
FILTER
AIN2+
AIN2-
REF2
24-BIT
ADC
DIGITAL
FILTER
AIN1+
AIN1-
REF1
24-BIT
ADC
DIGITAL
FILTER
AIN0+
AIN0-
REF0
REGISTERS AND
DIGITAL
CONTROL
SERIAL
INTERFACE
DOUT
DIN
SCLK
CS
CASCOUT
CASCIN
DRDYOUT
DRDYIN
SYNC
FAULT
OVRFLW
CLKOUT
XOUT
DGND
AGND
XIN
Functional Diagram
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