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參數資料
| 型號： | MAX1048BETX+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 26/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC/DAC 10BIT 36-TQFN-EP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | ADC，DAC |
| 分辨率（位）： | 10 b |
| 采樣率（每秒）： | 225k |
| 數據接口： | 串行 |
| 電壓電源： | 模擬和數字 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 36-TQFN 裸露焊盤（6x6） |
| 包裝： | 帶卷 (TR) |
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MAX1040/MAX1042/MAX1046/MAX1048
10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
32
______________________________________________________________________________________
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
ADC Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are ini-
tiated by writing a command byte to the conversion
register and are performed one at a time using SCLK
as the conversion clock. Scanning, averaging and the
FIFO are disabled, and the conversion result is avail-
able at DOUT during the conversion. Output data is
updated on the rising edge of SCLK in clock mode 11.
See Figure 9 for clock mode 11 timing.
Initiate a conversion by writing a command byte to the
conversion register followed by 16 SCLK cycles. If
CS
is pulsed high between the eighth and ninth cycles, the
pulse width must be less than 100s. To continuously
convert at 16 cycles per conversion, alternate 1 byte of
zeros (NOP byte) between each conversion byte. If 2
NOP bytes follow a conversion byte, the analog cells
power down at the end of the second NOP. Set the
FBGON bit to one in the reset register to keep the inter-
nal bias block powered.
If reference mode 00 is requested, or if an external refer-
ence is selected but a temperature measurement is being
requested, wait 45s with
CS high after writing the con-
version byte to extend the acquisition and allow the inter-
nal reference to power up. To perform a temperature
measurement, write 24 bytes (192 cycles) of zeros after
the conversion byte. The temperature result appears on
DOUT during the last 2 bytes of the 192 cycles.
Temperature results are available in 12-bit format.
Conversion-Time Calculations
The conversion time for each scan is based on a num-
ber of different factors: conversion time per sample,
samples per result, results per scan, if a temperature
measurement is requested, and if the external refer-
ence is in use. Use the following formula to calculate
the total conversion time for an internally timed conver-
sion in clock mode 00 and 10 (see the
Electrical
Characteristics, as applicable):
Total conversion time =
tCNV x nAVG x nSCAN + tTS + tINT-REF,SU
where:
tCNV = tDOV (where tDOV is dependent on clock mode
and reference mode selected)
nAVG = samples per result (amount of averaging)
nSCAN = number of times each channel is scanned; set
to one unless [SCAN1, SCAN0] = 10
tTS = time required for temperature measurement
(53.1s); set to zero if temperature measurement is not
requested
tINT-REF,SU = tWU (external-reference wake-up); if a
conversion using the external reference is requested
In clock mode 01, the total conversion time depends on
how long
CNVST is held low or high. Conversion time in
externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long
CS is held
high between each set of eight SCLK cycles. In clock
mode 01, the total conversion time does not include the
time required to turn on the internal reference.
SCLK
DOUT
X = DON'T CARE.
MSB1
LSB1
MSB2
(ACQUISITION1)
(ACQUISITION2)
(CONVERSION1)
DIN
(CONVERSION BYTE)
CS
EOC
Figure 9. Clock Mode 11—Externally Timed Acquisition, Sampling, and Conversion without
CNVST
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