參數資料
型號： MA330012
廠商： Microchip Technology
文件頁數： 168/199頁
文件大小： 0K
描述： MODULE DSPIC33 100P TO 84QFP
標準包裝： 1
附件類型： 插拔式模塊（PIM）80p - dsPIC33FJ256GP710
適用于相關產品： dsPICDEM（DM300019）
產品目錄頁面： 658 (CN2011-ZH PDF)
相關產品： DSPIC33FJ64GP710T-I/PT-ND - IC DSPIC MCU/DSP 64K 100TQFP
DSPIC33FJ64GP710T-I/PF-ND - IC DSPIC MCU/DSP 64K 100TQFP
DSPIC33FJ64GP310T-I/PT-ND - IC DSPIC MCU/DSP 64K 100TQFP
DSPIC33FJ64GP310T-I/PF-ND - IC DSPIC MCU/DSP 64K 100TQFP
DSPIC33FJ256GP510T-I/PT-ND - IC DSPIC MCU/DSP 256K 100TQFP
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DSPIC33FJ128GP310T-I/PT-ND - IC DSPIC MCU/DSP 128K 100TQFP
DSPIC33FJ128GP310T-I/PF-ND - IC DSPIC MCU/DSP 128K 100TQFP
DSPIC33FJ256GP710T-I/PT-ND - IC DSPIC MCU/DSP 256K 100TQFP
DSPIC33FJ256GP710T-I/PF-ND - IC DSPIC MCU/DSP 128K 100TQFP
更多...
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dsPIC33F
DS70165E-page 68
Preliminary
2007 Microchip Technology Inc.
TABLE 3-35:
FUNDAMENTAL ADDRESSING MODES SUPPORTED
3.3.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
Addressing modes supported by most MCU instruc-
tions, move and accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
In summary, the following Addressing modes are
supported by move and accumulator instructions:
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
3.3.4
MAC
INSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC
, MAC, MPY, MPY.N, MOVSAC and MSC), also referred
to as MAC instructions, utilize a simplified set of address-
ing modes to allow the user to effectively manipulate the
data pointers through register indirect tables.
The 2-source operand prefetch registers must be
members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU
and W10 and W11 will always be directed to the Y
AGU. The effective addresses generated (before and
after modification) must, therefore, be valid addresses
within X data space for W8 and W9 and Y data space
for W10 and W11.
In summary, the following addressing modes are
supported by the MAC class of instructions:
Register Indirect
Register Indirect Post-Modified by 2
Register Indirect Post-Modified by 4
Register Indirect Post-Modified by 6
Register Indirect with Register Offset (Indexed)
3.3.5
OTHER INSTRUCTIONS
Besides the various addressing modes outlined above,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit signed
literals to specify the branch destination directly, whereas
the DISI instruction uses a 14-bit unsigned literal field. In
some instructions, such as ADD Acc, the source of an
operand or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.
3.4
Modulo Addressing
Modulo Addressing mode is a method of providing an
automated means to support circular data buffers using
hardware. The objective is to remove the need for soft-
ware to perform data address boundary checks when
executing tightly looped code, as is typical in many
DSP algorithms.
Modulo Addressing can operate in either data or program
space (since the data pointer mechanism is essentially
the same for both). One circular buffer can be supported
in each of the X (which also provides the pointers into
program space) and Y data spaces. Modulo Addressing
can operate on any W register pointer. However, it is not
Addressing Mode
Description
File Register Direct
The address of the file register is specified explicitly.
Register Direct
The contents of a register are accessed directly.
Register Indirect
The contents of Wn forms the EA.
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented or
decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
Register Indirect with Literal Offset
The sum of Wn and a literal forms the EA.
Note:
For the MOV instructions, the Addressing
mode specified in the instruction can differ
for
the
source
and
destination
EA.
However, the 4-bit Wb (Register Offset)
field is shared between both source and
destination (but typically only used by
one).
Note:
Not
all
instructions
support
all
the
Addressing modes given above. Individual
instructions may support different subsets
of these Addressing modes.
Note:
Register Indirect with Register Offset
Addressing mode is only available for W9
(in X space) and W11 (in Y space).
相關PDF資料
PDF描述
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AIMC-0805-1N8S-T INDUCTOR MULTILAYER 1.8NH 0805
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相關代理商/技術參數
參數描述
MA330013 功能描述:子卡和OEM板 dsPIC33F Plug In Module RoHS:否 制造商:BeagleBoard by CircuitCo 產品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
MA330014 功能描述:子卡和OEM板 dsPIC33 MC RoHS:否 制造商:BeagleBoard by CircuitCo 產品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
MA330015 功能描述:子卡和OEM板 dsPIC33 GP RoHS:否 制造商:BeagleBoard by CircuitCo 產品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
MA330016 功能描述:子卡和OEM板 dsPIC33F GP RoHS:否 制造商:BeagleBoard by CircuitCo 產品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
MA330017 功能描述:子卡和OEM板 dsPIC33F MC RoHS:否 制造商:BeagleBoard by CircuitCo 產品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
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