參數(shù)資料
型號(hào)： MA330011
廠(chǎng)商： Microchip Technology
文件頁(yè)數(shù)： 45/199頁(yè)
文件大?。?/td> 0K
描述： MODULE DSPIC33 100P TO 100QFP
標(biāo)準(zhǔn)包裝： 1
附件類(lèi)型： 插拔式模塊（PIM）- dsPIC33FJ256GP710
適用于相關(guān)產(chǎn)品： Explorer 16（DM240001 或 DM240002）
產(chǎn)品目錄頁(yè)面： 658 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： DSPIC33FJ64GP710T-I/PT-ND - IC DSPIC MCU/DSP 64K 100TQFP
DSPIC33FJ64GP710T-I/PF-ND - IC DSPIC MCU/DSP 64K 100TQFP
DSPIC33FJ64GP310T-I/PT-ND - IC DSPIC MCU/DSP 64K 100TQFP
DSPIC33FJ64GP310T-I/PF-ND - IC DSPIC MCU/DSP 64K 100TQFP
DSPIC33FJ256GP510T-I/PT-ND - IC DSPIC MCU/DSP 256K 100TQFP
DSPIC33FJ256GP510T-I/PF-ND - IC DSPIC MCU/DSP 256K 100TQFP
DSPIC33FJ128GP310T-I/PT-ND - IC DSPIC MCU/DSP 128K 100TQFP
DSPIC33FJ128GP310T-I/PF-ND - IC DSPIC MCU/DSP 128K 100TQFP
DSPIC33FJ256GP710T-I/PT-ND - IC DSPIC MCU/DSP 256K 100TQFP
DSPIC33FJ256GP710T-I/PF-ND - IC DSPIC MCU/DSP 128K 100TQFP
更多...
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2007 Microchip Technology Inc.
Preliminary
DS70165E-page 137
dsPIC33F
write collision (PWCOLx) status bits in a DMAC Status
register (DMACS0) to allow the DMAC error trap
handler to determine the source of the Fault condition.
7.2.1
BYTE OR WORD TRANSFER
Each DMA channel can be configured to transfer
words or bytes. As usual, words can only be moved to
and from aligned (even) addresses. Bytes can be
moved to or from any (legal) address.
If the SIZE bit (DMAxCON<14>) is clear, word sized
data is transferred. The LSb of the DMA RAM Address
register (DMAxSTA or DMAxSTB) is ignored. If
Post-Increment Addressing mode is enabled, the DMA
RAM Address register is incremented by 2 after every
word transfer.
If the SIZE bit is set, byte sized data is transferred. If
Post-Increment Addressing is enabled, the DMA RAM
Address register is incremented by 1 after every byte
transfer.
7.2.2
ADDRESSING MODES
The DMAC supports Register Indirect and Register
Indirect Post-Increment Addressing modes for DMA
RAM addresses (source or destination). Each channel
can select the DMA RAM Addressing mode indepen-
dently. The Peripheral SFR is always accessed using
Register Indirect Addressing.
If the AMODE<1:0> bits (DMAxCON<5:4>) are set to
‘01’,
Register
Indirect
Addressing
without
Post-Increment is used, which implies that the DMA
RAM address remains constant.
If the AMODE<1:0> bits are clear, DMA RAM is
accessed using Register Indirect Addressing with
Post-Increment, which means the DMA RAM address
will be incremented after every access
Any DMA channel can be configured to operate in
Peripheral Indirect Addressing mode by setting the
AMODE<1:0> bits to ‘10’. In this mode, the DMA RAM
source or destination address is partially derived from
the peripheral as well as the DMA Address registers.
Each peripheral module has a pre-assigned peripheral
indirect address which is logically ORed with the DMA
Start Address register to obtain the effective DMA RAM
address. The DMA RAM Start Address register value
must be aligned to a power-of-two boundary.
7.2.3
DMA TRANSFER DIRECTION
Each DMA channel can be configured to transfer data
from a peripheral to DMA RAM, or from DMA RAM to a
peripheral.
If the DIR bit (DMAxCON<13>) is clear, the reads
occur from a peripheral SFR (using the DMA Periph-
eral Address register, DMAxPAD) and the writes are
directed to the DMA RAM (using the DMA RAM
Address register).
If the DIR bit (DMAxCON<13>) is set, the reads occur
from the DMA RAM (using the DMA RAM Address
register) and the writes are directed to the peripheral
(using
the
DMA
Peripheral
Address
register,
DMAxPAD).
7.2.4
NULL DATA PERIPHERAL WRITE
MODE
If the NULLW bit (DMAxCON<11>) is set, a null data
write to the peripheral SFR is performed in addition to
a data transfer from the peripheral SFR to DMA RAM
(assuming the DIR bit is clear). This mode is most use-
ful in applications in which sequential reception of data
is required without any data transmission
Note:
DMAxCNT value is independent of data
transfer size (byte/word). If an address off-
set is required, a 1-bit left shift of the
counter is required to generate the correct
offset for (aligned) word transfers.
Note:
Only the ECAN and ADC modules can use
Peripheral Indirect Addressing
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MA330011 制造商:Microchip Technology Inc 功能描述:dsPIC33 GP 100P to 100P TQFP Plug-In Mod
MA330012 功能描述:子卡和OEM板 dsPIC33F GP 100P to 84P Plug In Module RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
MA330013 功能描述:子卡和OEM板 dsPIC33F Plug In Module RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
MA330014 功能描述:子卡和OEM板 dsPIC33 MC RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
MA330015 功能描述:子卡和OEM板 dsPIC33 GP RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
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