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參數(shù)資料
| 型號(hào)： | M68AW031AL70NS1U |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | SRAM |
| 英文描述： | 32K X 8 STANDARD SRAM, 70 ns, PDSO28 |
| 封裝： | 8 X 13.40 MM, PLASTIC, REVERSE, TSOP-28 |
| 文件頁(yè)數(shù)： | 19/21頁(yè) |
| 文件大小： | 398K |
| 代理商： | M68AW031AL70NS1U |
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Obsolete
Product(s)
- Obsolete
7/21
M68AW031A
OPERATION
The M68AW031A has a Chip Enable power down
feature which invokes an automatic standby mode
whenever Chip Enable is de-asserted (E = High).
An Output Enable (G) signal provides a high
speed tri-state control, allowing fast read/write cy-
cles to be achieved with the common I/O data bus.
Operational modes are determined by device con-
trol inputs W and E as summarized in the Operat-
ing Modes table (see Table 2.).
Read Mode
The M68AW031A is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, and Chip Enable (E) is asserted. This pro-
vides access to data of the 262,144 locations in
the static memory array, specified by the 15 ad-
dress inputs. Valid data will be available at the
eight output pins within tAVQV after the last stable
address, providing G is Low and E is Low. If Chip
Enable or Output Enable access times are not
met, data access will be measured from the limit-
ing parameter (tELQV or tGLQV) rather than the ad-
dress. Data out may be indeterminate at tELQX and
tGLQX but data lines will always be valid at tAVQV.
Read mode AC timings and Characteristics.
Write Mode
The M68AW031A is in the Write mode whenever
the W and E are Low. Either the Chip Enable input
(E) or the Write Enable input (W) must be de-
asserted
during
Address
transitions
for
subsequent write cycles. When E (W) is Low, write
cycle begins on the W (E)'s falling edge.
Therefore, address setup time is referenced to
Write Enable or Chip Enable as tAVWL and tAVEL
respectively, and is determined by the latter
occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E or W.
If the Output is enabled (E = Low, G = Low), then
W will return the outputs to high impedance within
tWLQZ of its falling edge. Care must be taken to
avoid bus contention in this type of operation. Data
input must be valid for tDVWH before the rising
edge of Write Enable, or for tDVEH before the rising
edge of E, whichever occurs first, and remain valid
for tWHDX and tEHDX respectively.
Write mode AC timings and Characteristics.
Table 2. Operating Modes
Note: X = VIH or VIL.
Operation
E
W
G
DQ0-DQ7
Power
Deselected
VIH
XX
Hi-Z
Standby (ISB)
Read
VIL
VIH
VIL
Data Output
Active (ICC)
Write
VIL
X
Data Input
Active (ICC)
Output Disabled
VIL
VIH
Hi-Z
Active (ICC)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M68AW031AM70NS1T | 32K X 8 STANDARD SRAM, 70 ns, PDSO28 |
| M68AW256MN70ND6E | 256K X 16 STANDARD SRAM, 70 ns, PDSO44 |
| M68AW256ML70ZH6E | 256K X 16 STANDARD SRAM, 70 ns, PBGA48 |
| M74HC08RM13TR | QUAD 2-INPUT AND GATE |
| M74HC244-1DWP | Dual 4-Bit Non-Inverting Buffer/Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M68AW031AL70NS6U | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit (32K x8) 3.0V Asynchronous SRAM |
| M68AW031AM55MS6T | 制造商:STMicroelectronics 功能描述: |
| M68AW031AM70MS6T | 制造商:STMicroelectronics 功能描述: |
| M68AW031AM70MS6U | 制造商:STMicroelectronics 功能描述: |
| M68AW031AM70N6 | 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 WIRELESS FLASH RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問(wèn)時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
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