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參數(shù)資料
| 型號： | M68AR256ML70ZB1F |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | SRAM |
| 英文描述： | 256K X 16 STANDARD SRAM, 70 ns, PBGA48 |
| 封裝： | 6 X 7 MM, 0.75 MM PITCH, LEAD FREE, TFBGA-48 |
| 文件頁數(shù)： | 19/21頁 |
| 文件大?。?/td> | 414K |
| 代理商： | M68AR256ML70ZB1F |
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M68AR256M
OPERATION
The M68AR256M has four standard operating
modes: Output Disabled, Read, Write and Stand-
by/Power-Down. These modes are determined by
the control inputs G, W, E, LB and UB as summa-
rized in Table 2., Operating Modes.
Output Disabled. The Output Enable signal, G,
provides high-speed tri-state control of DQ0-
DQ15, allowing fast read/write cycles on the com-
mon I/O data bus. The device is in Output Dis-
abled mode when Output Enable, G, is High. In
this mode, LB and UB are Don’t care and DQ0-
DQ15 are high impedance.
Read Mode. Read operations are used to output
the contents of the SRAM Array. The M68AR256M
is in the Read mode whenever Write Enable (W) is
High, VIH, with Output Enable (G) Low, VIL, Chip
Enables (E) is asserted and at least one of the
Byte Enable inputs, UB and LB, is at VIL.
If only one of the Byte Enable inputs (UB or LB), is
at VIL, the M68AR256M is in Byte Read mode. If
the two Byte Enable inputs (UB or LB) are at VIL,
the M68AR256M is in Word Read mode. So de-
pending on the status of the UB and LB signals,
valid data will be available on the lower eight, the
upper eight or all sixteen output pins, tAVQV after
the last stable address providing G is Low and E is
Low.
If either of E, G and UB/LB is asserted after tAVQV
has elapsed, data access will be measured from
the limiting parameter (tELQV, tGLQV or tBLQV) rath-
er than the address.Data out may be indetermi-
nate at tELQX, tGLQX and tBLQX, but data lines will
always be valid at tAVQV.
Write Mode. Write operations are used to write
data to the SRAM. The M68AR256M is in the
Write mode whenever the W and E are Low, VIL.
Either the Chip Enable input (E) or the Write
Enable input (W) must be de-asserted during
Address transitions for subsequent write cycles.
When E (W) is Low, and UB or LB is Low, write
cycle begins on the falling edge of W (E). When E
and W are Low, and UB = LB = High, write cycle
begins on the first falling edge of UB or LB.
Therefore, address setup time is referenced to
Write Enable, Chip Enable or UB/LB as tAVWL,
tAVEL and tAVBL respectively, and is determined by
the latter occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E, W or UB/LB.
If the Output is enabled (E = Low, G = Low, LB or
UB = Low), then W will return the outputs to high
impedance within tWLQZ of its falling edge. Care
must be taken to avoid bus contention in this type
of operation. Data input must be valid for tDVWH
before the rising edge of Write Enable, or for tDVEH
before the rising edge of E, or for tDVBH before the
rising edge of UB/LB whichever occurs first, and
remain valid for tWHDX, tEHDX and tBHDX respec-
tively.
Standby/Power-Down Mode. The M68AR256M
has a Chip Enable Power-Down feature which in-
vokes an automatic standby mode whenever ei-
ther Chip Enable is de-asserted (E = High) or LB
and UB are de-asserted (LB and UB = High).
An Output Enable (G) signal provides a high
speed tri-state control, allowing fast read/write cy-
cles to be achieved with the common I/O data bus.
Operational modes are determined by device con-
trol inputs W, E, LB and UB as summarized in the
Operating Modes table (see Table 2).
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