參數(shù)資料
型號: M66239FP
廠商: Renesas Technology Corp.
英文描述: High Speed Standard Clock Generator With Frequency Synthesizer
中文描述: 高速標(biāo)準(zhǔn)時(shí)鐘發(fā)生器,頻率合成器
文件頁數(shù): 9/24頁
文件大小: 312K
代理商: M66239FP
M66239FP
Rev.1.00 Mar 16, 2005 page 17 of 23
Frequency Modulation Resister Setting (Read Operation)
Read Operation
After write operation completed, it can confirm the resister status using read operation to serial input resister.
When SENABLE is "L" level, SDATAIN is written to serial input resister by SCLK. SDATAIN is composed by 4 bit
address + 3 bit W/R distinction data. After SENABLE change to "H", more than 20 dummy SLCK cycle is needed.
tDS
tDH
tDS
tDH
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
SENABLE
SCLK
SDATAIN
A0
A1
A2
A3
L
SDATAOUT
D0
D1
D2
D13 D14 D15
LSB
MSB
4bit address
20 cycles dummy input
16bit data
For write operation, set to "L" 3 cycles continuously.
Figure 10 Frequency Modulation Resister Setting (Read Operation)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M66239FP(#RB0S) 制造商:Renesas Electronics Corporation 功能描述:
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