參數(shù)資料
型號(hào): M66239FP
廠商: Renesas Technology Corp.
英文描述: High Speed Standard Clock Generator With Frequency Synthesizer
中文描述: 高速標(biāo)準(zhǔn)時(shí)鐘發(fā)生器,頻率合成器
文件頁(yè)數(shù): 8/24頁(yè)
文件大?。?/td> 312K
代理商: M66239FP
M66239FP
Rev.1.00 Mar 16, 2005 page 16 of 23
Frequency Modulation Resister
Resister
Name
Function
Default Value
Address
Bit
Number
Setting Range
Resister 1
0000
0001
Operation
mode
min
max
0000000000000001
0000000000000100
A3
A0
D15
D0
Unit 1LSB
0000000000000001(1 dec)
Resister 2
MCLK cycle
min
max
0000010111011100
1111111111111111
0010000000000000(8192 dec)
D15
* Mode1 when 1 dec
0000000011111111(255 dec)
Resister 4
0 0 1 1
Center
frequency
min
max
0000000000000000
0000000111111111
0000000100000000(256 dec)
* 0% when 256 dec
* Modulate to + side more than 256 dec
* Modulate to – side less than 256 dec
* –2.55% when min. value
* +2.55% when max. value
Modulation
period
Resister 6
0101
MCLK cycle
min
max
0000000111110100
1001111111111111
0000011001100110(1638 dec)
1st-pole
position
Resister 5
0 1 0 0
Peak
frequency
min
max
0000000000011110
0000000011111111
* ±0.30% when min. value
* ±2.55% when max. value
0000000010000000(128 dec)
Resister 7
0 1 1 0
MCLK cycle
min
max
0000000111110100
1001111111111111
0000110011001100(3276 dec)
2nd-pole
position
Resister 8
0 1 1 1
MCLK cycle
min
max
0000000111110100
1001111111111111
0001001100110010(4914 dec)
3rd-pole
position
Resister 9
1 0 0 0
MCLK cycle
min
max
0000000111110100
1001111111111111
0001100110011000(6552 dec)
4th-pole
position
Resister 3
0 0 1 0
MCLK cycle
MCLK frequency
×0.01%
Resister 10
1 0 0 1
1st-pole
frequency
(Mode 4)
min
max
0000000000000000
0000000111111111
* –2.55% when min. value
* +2.55% when max. value
MCLK frequency
×0.01%
0000000110000000(384 dec)
* +1.28% when 384 dec
* –1.28% when 128 dec
* ±2.55% when 255 dec
Resister 11
1010
3rd-pole
frequency
(Mode 4)
min
max
0000000000000000
0000000111111111
* –2.55% when min. value
* +2.55% when max. value
0000000000000000(0 dec)
* 0.01% mode when 0 dec
Resister 12
1 0 1 1
Modulation
resolution
min
max
0000000000000000
0000000000000001
* ±0.01% mode when min.
* ±0.005% mode when max.
0000000000000000(0 dec)
* Delay 0 when 0 dec
Resister 13
1 1 0 0
Output phase
control
3 bit
16 bit
9 bit
16 bit
8 bit
16 bit
10 bit
9 bit
1 bit
3 bit
min
max
0000000000000000
0000000000000111
* Delay 0 when min.
* Delay 7T/8 when max.
MCLK frequency
×0.01%
T/8
(Clock cycle)
MCLK frequency
×0.01%
min
max
0000000001100100
0000001111111111
0000000100000000(256 dec)
Modulation
start position
Notes: 1.
2.
3.
4.
5.
6.
Set to the following value for resister 1.
For operation mode 1: "0000000000000001"
For operation mode 2: "0000000000000010"
For operation mode 3: "0000000000000011"
For operation mode 4: "0000000000000100"
Resister 12 must not change.
Above table intend to setting available value of resister, practical limits are described in page 20.
Resister 13 is for phase control of sync clock output.
If the default value of above resister use, write operation to all resister must be done.
Resister 6 to 9 refer to following.
1st Pole = Tspace1
2nd Pole = Tspace1 + Tspace2
3rd Pole = Tspace1 + Tspace2 + Tspace3
4th Pole = Tspace1 + Tspace2 + Tspace3 + Tspace4
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