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參數(shù)資料
| 型號： | M5M4V4265CTP-5S |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | APUS MFR4200 PBFREE |
| 中文描述： | 江戶（超頁）模式4194304位（262144字由16位）動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 4/31頁 |
| 文件大?。?/td> | 311K |
| 代理商： | M5M4V4265CTP-5S |
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EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
MITSUBISHI LSIs
M5M4V4265CJ,TP-5,-5S:under development
4
CAPACITANCE
(Ta=0~70C, V
CC
=3.3±0.3V, V
SS
=0V, unless otherwise noted)
Limits
Typ
Min
Max
5
7
Unit
pF
pF
pF
Input capacitance, address inputs
Input capacitance, clock inputs
Input/Output capacitance, data ports
C
I (A)
C
I (CLK)
C
I / O
Symbol
Parameter
Test conditions
7
V
I
=V
SS
f=1MHz
V
I
=25mVrms
SWITCHING CHARACTERISTICS
(Ta=0~70C, V
CC
=3.3±0.3V, Vss=0V, unless otherwise noted, see notes 6,14,15)
Access time from CAS
Access time from RAS
Columu address access time
Access time from CAS precharge
Access time from OE
Output hold time from CAS
Output hold time from RAS
t
CAC
t
RAC
t
AA
t
CPA
t
OEA
t
OHC
t
OHR
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
15
60
30
33
15
15
15
t
CLZ
t
OEZ
t
WEZ
Output low impedance time from CAS low
Output disable time after OE high
Output disable time after WE high
Output disable time after CAS high
Output disable time after RAS high
(Note 7,8)
(Note 7,9)
(Note 7,10)
(Note 7,11)
(Note 7)
(Note 13)
5
t
OFF
t
REZ
(Note 12)
(Note 12)
(Note 12,13)
(Note 7)
15
15
ns
ns
20
70
35
38
20
20
20
20
20
(Note 13)
(Note 12,13)
ns
5
5
5
5
Note 6 : An initial pause of 500μs is required after power-up followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh
cycles).
Note the RAS may be cycled during the initial pause. And 8 initialization cycles are required after prolonged periods (greater than 8.2ms) of RAS
inactivity before proper device operation is achieved.
7 : Measured with a load circuit equivalent to 50pF, V
OH
(I
OH
=-2mA) and V
OL
(I
OL
=2mA). The reference levels for measuring of output signals are
2.0V(V
OH
) and 0.8V(V
OL
).
8 : Assumes that
t
RCD
≥
t
RCD(max)
and
t
ASC
≥
t
ASC(max)
and
t
CP
≥
t
CP(max).
9 : Assumes that
t
RCD
≤
t
RCD(max)
and
t
RAD
≤
t
RAD(max)
. If
t
RCD
or
t
RAD
is greater than the maximum recommended value shown in this table,
t
RAC
will increase by amount that
t
RCD
exceeds the value shown.
10 : Assumes that
t
RAD
≥
t
RAD(max)
and
t
ASC
≤
t
ASC(max)
.
11 : Assumes that
t
CP
≤
t
CP(max)
and
t
ASC
≥
t
ASC(max)
.
12 :
t
OEZ (max)
,
t
WEZ(max)
,
t
OFF(max)
and
t
REZ(max)
defines the time at which the output achieves the high impedance state (I
OUT
≤
±5μA ) and is not
reference to V
OH(min)
or V
OL(max)
.
13 : Output is disabled after both RAS and CAS go to high.
5
13
50
25
28
13
13
13
13
13
Limits
Parameter
Symbol
Unit
Min
Max
Min
Max
M5M4V4265C-6,-6S
M5M4V4265C-7,-7S
Min
Max
M5M4V4265C-5,-5S
5
5
相關PDF資料 |
PDF描述 |
|---|---|
| M5M4V4265CTP-6 | EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| M5M4V4265CTP-6S | EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| M5M4V4265CTP-7 | EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| M5M4V4265CTP-7S | EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| M5M4V4405CJ | EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V4265CTP-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| M5M4V4265CTP-6S | 制造商:Mitsubishi Electric 功能描述:256K X 16 EDO DRAM, 60 ns, PDSO40 |
| M5M4V4265CTP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| M5M4V4265CTP-7S | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| M5M4V4405CJ | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM |
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