
EDEDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
MIMITSUBISHI LSIs
M5M4V4265CJ,TP-5,-5S:under development
1
DESCRIPTION
This is a family of 262144-word by 16-bit dynamic RAMs with EDO
mode fuction, fabricated with the high performance CMOS
process, and is ideal for the buffer memory systems of personal
computer graphics and HDD where high speed, low power
dissipation, and low costs are essential. The use of double-layer
metalization process technology and a single-transistor dynamic
storage stacked capacitor cell provide high circuit density at
reduced costs. The lower supply (3.3V) operation, due to the
optimization of transistor structure, provides low power dissipation
while maintaining high speed operation. Multiplexed address inputs
permit both a reduction in pins and an increase in system
densities. Self or extended refresh current is low enough for
battery back-up application. This device has 2CAS and 1W
terminals with a refresh cycle of 512 cycles every 8.2ms.
APPLICATION
Microcomputer memory, Refresh memory for CRT, Frame buffer
memory for CRT
PIN CONFIGURATION (TOP VIEW)
NC : NO CONNECTION
M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S
PIN DESCRIPTION
Pin name
A
0
~A
8
DQ
1
~DQ
16
RAS
V
CC
V
SS
UCAS
W
OE
Function
Address inputs
Data inputs / outputs
Row address strobe input
Lower byte control
column address strobe input
Upper byte control
column address strobe input
Write control input
Output enable input
Power supply (+3.3V)
Ground (0V)
LCAS
Outline 44P3W-R (400mil TSOP Nomal Bend)
1
9
2
3
4
5
13
10
14
15
44
43
42
41
40
32
36
35
31
30
DQ
1
A
0
A
1
A
2
A
3
(3.3V)V
CC
V
S
S(0V)
NC
A
8
A
7
A
6
A
5
A
4
W
RAS
UCAS
OE
6
7
8
39
38
37
18
20
19
21
22
16
17
27
25
26
24
23
29
28
DQ
2
DQ
3
DQ4
DQ
5
DQ
6
DQ
7
DQ
8
(3.3V)V
CC
(3.3V)V
CC
NC
NC
LCAS
NC
DQ
12
DQ
11
DQ
10
DQ
9
V
SS
(0V)
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
(0V)
Standard 40 pin SOJ, 44 pin TSOP (II)
Single 3.3±0.3V supply
Low stand-by power dissipation
CMOS Input level 1.8mW (Max)
CMOS Input level 360μW (Max) *
Operating power dissipation
M5M4V4265CXX-5,-5S 486mW (Max)
M5M4V4265CXX-6,-6S 432mW (Max)
M5M4V4265CXX-7,-7S 396mW (Max)
Self refresh capability *
Self refresh current 100μA (Max)
Extended refresh capability
Extended refresh current 100μA (Max)
EDO mode (512-column random access), Read-modify-write, RAS-
only refresh, CAS before RAS refresh, Hidden refresh capabilities.
Early-write mode, OE and W to control output buffer impedance
512 refresh cycles every 8.2ms (A
0
~A
8
)
512 refresh cycles every 128ms (A
0
~A
8
) *
Byte or word control for Read/Write operation (2CAS, 1W type)
* : Applicable to self refresh version (M5M4V4265CJ,TP-5S,-6S,
-7S : option) only
FEATURES
Type name
RAS
(time
50
aCAS
(time
13
(time
25
access
time
(min.ns)
90
Cycle
Ption
(typ.mW)
408
M5M4V4265CXX-7,-7S
XX=TP,J
M5M4V4265CXX-6,-6S
60
70
15
20
30
35
110
130
363
333
15
20
aOE
(time
13
M5M4V4265CXX-5,-5S
Outline 40P0K (400mil SOJ)
1
9
2
3
4
5
11
10
12
13
40
39
38
37
36
30
32
31
29
28
DQ
1
A
0
A
1
A
2
A
3
(3.3V)V
CC
V
S
S(0V)
NC
A
8
A
7
A
6
A
5
A
4
W
RAS
UCAS
OE
6
7
8
35
34
33
16
18
17
19
20
14
15
25
23
24
22
21
27
26
DQ
2
DQ
3
DQ4
DQ
5
DQ
6
DQ
7
DQ
8
(3.3V)V
CC
(3.3V)V
CC
NC
NC
LCAS
NC
DQ
12
DQ
11
DQ
10
DQ
9
V
SS
(0V)
DQ
16
DQ
15
DQ
14
DQ
13
V
SS
(0V)