參數(shù)資料
型號(hào)： M5M44405CJ-7S
廠商： Mitsubishi Electric Corporation
英文描述： EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
中文描述： 江戶（超頁(yè)模式）4194304位（1048576 - Word的4位）動(dòng)態(tài)隨機(jī)存儲(chǔ)器
文件頁(yè)數(shù)： 26/27頁(yè)
文件大?。?/td> 244K
代理商： M5M44405CJ-7S
EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
M5M44405CJ,TP-5,-6,-7,-5S,-6S,-7S
MITSUBISHI LSIs
M5M44405CJ,TP-5,-5S:Under development
Switching from self refresh operation to read/write operation.
The time interval from the rising edge of RAS signal at the end of
self refresh operation to the falling edge of RAS signal in the first
CBR refresh cycle during read/write operation period should be
set within t
SND
(shown in table 2)
Note 30 : Self refresh sequence
Two refreshing methods should be used properly depending on the
low pulse width(t
RASS
) of RAS signal during self refresh period.
1. Distributed refresh during Read/Write operation
(A) Timing Diagram
t
NSD
t
RASS
≥
100μs
t
SND
RAS
26
Switching from read/write operation to self refresh operation.
The time interval from the falling edge of RAS signal in the last
CBR refresh cycle during read/write operation period to the falling
edge of RAS signal at the start of self refresh operation should be
set within t
NSD
(shown in table 2).
1.1 CBR distributed refresh
Definition of CBR distributed refresh
(Including extended refresh)
The CBR distributed refresh performs more than 1024
constant period (125μs max.) CBR cycles within 128ms.
All combinations of nine row address signals (A
0
~A
9
) are
selected during 1024 constant period (16μs max.) RAS
only refresh cycles within 16.4ms.
Definition of RAS only distributed refresh
Note: Switching from read/write operation to self refresh operation.
Hidden refresh may be used instead of CBR refresh.
RAS/CAS refresh may be used instead of RAS only refresh.
1.2 RAS only distributed refresh
The time interval t
NSD
from the falling edge of RAS signal in the
last RAS only refresh cycle during read/write operation period to
the falling edge of RAS signal at the start of self refresh operation
should be set within 16μs.
Switching from self refresh operation to read/write operation.
The time interval t
SND
from the rising edge of RAS signal at the
end of self refresh operation to the falling edge of RAS signal in
the first CBR refresh cycle during read/write operation period
should be set within 16μs.
Read /Write Cycle
Self Refresh Cycle
Read /Write Cycle
last
refresh cycle
first
refresh cycle
Table 2
t
NSD
≤
16μs
t
SND
≤
16μs
t
NSD
≤
125μs
t
SND
≤
125μs
Read/Write Cycle
CBR distributed
refresh
RAS only
distributed refresh
Read/Write
Self Refresh
Self Refresh
Read/Write
(B) Definition of distributed refresh
t
REF
t
REF
/1024
RAS
t
REF
/1024
refresh
cycle
read/write
cycles
read/write
cycles
refresh
cycle
refresh
cycle
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M5M44405CTP-5 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
M5M44405CTP-5S 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
M5M44405CTP-6 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
M5M44405CTP-6S 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
M5M44405CTP-7 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO ( HYPER PAGE MODE ) 4194304-BIT ( 1048576-WORD BY 4-BIT ) DYNAMIC RAM
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