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參數(shù)資料
| 型號： | M5LV-512/160-12YI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | Fifth Generation MACH Architecture |
| 中文描述： | EE PLD, 12 ns, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 19/42頁 |
| 文件大?。?/td> | 938K |
| 代理商： | M5LV-512/160-12YI |
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26
MACH 5 Family
1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modied where
these parameters may be affected.
ICC vs. FREQUENCY
These curves represent the typical power consumption for a particular device at system frequency.
The selected “typical” pattern is a 16-bit up-down counter. This pattern lls the device and
exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type
register. Power/Speed are optimized to obtain the highest counter frequency and the lowest
power. The highest frequency (LSBs) is placed in common PAL blocks, which are set to high
power. The lowest frequency signals (MSBs) are placed in a common PAL block and set to
lowest power. For a more detailed discussion about MACH 5 power consumption, refer to the
application note entitled MACH 5 Power in the Application Notes section on the Lattice Data Book
CD-ROM or Lattice web site.
ICC CURVES AT HIGH /LOW POWER MODES
CAPACITANCE1
Parameter Symbol
Parameter
Description
Test conditions
Typ
Unit
CIN
I/CLK pin
VIN =2.0 V
3.3 V or 5 V, 25 C, 1 MHz
12
pF
CI/O
I/O pin
VOUT =2.0 V
3.3 V or 5 V, 25 C, 1 MHz
10
pF
700
600
500
400
300
200
100
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
VCC = 5 V or 3.3 V, TA = 25 C
M5(LV)-512 high power
M5(LV)-384 high power
M5(LV)-320 high power
M5-256/1 and
M5LV-25 high power
M5-128/1 and M5LV-128 high power
M5(LV)-384 low power
M5(LV)-320 low power
M5-256/1 and M5LV-256 low power
M5-128/1 and M5LV-128 low power
I CC
(mA)
Frequency (MHz)
20446G-048
Figure 8. ICC Curves at High/Low Power Modes
M5-192/1 high power
M5-192/1 low power
M5(LV)-512 low power
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