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參數(shù)資料
| 型號(hào)： | M59MR032D120ZC6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 32 Mbit 2Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory |
| 中文描述： | 32兆位的2Mb x16插槽，復(fù)用的I / O，雙行，突發(fā)1.8V電源快閃記憶體 |
| 文件頁(yè)數(shù)： | 35/49頁(yè) |
| 文件大?。?/td> | 352K |
| 代理商： | M59MR032D120ZC6T |
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M59MR032C, M59MR032D
40/49
Table 34. Program, Erase Times and Program, Erase Endurance Cycles
(TA = 0 to 70°C; VDD = VDDQ = 1.65V to 2.0V, VPP = VDD unless otherwise specified)
Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or
erase should perform significantly better.
2. Excludes the time needed to execute the sequence for program instruction.
3. Same timing value if
VPP = 12V.
Table 35. Data Polling and Toggle Bits AC Characteristics (1)
(TA = –40 to 85 °C; VDD = VDDQ = 1.65V to 2.0V)
Note: 1. All other timings are defined in Read AC Characteristics table.
Parameter
Min
Max (1)
Typ
Typical after
100k W/E Cycles
Unit
Parameter Block (4 KWord) Erase (Preprogrammed)
2.5
0.15
0.4
sec
Main Block (32 KWord) Erase (Preprogrammed)
10
1
3
sec
Bank Erase (Preprogrammed, Bank A)
2
6
sec
Bank Erase (Preprogrammed, Bank B)
10
30
sec
Chip Program (2)
20
25
sec
Chip Program (DPG, VPP = 12V)
(2)
10
sec
Word Program (3)
200
10
s
Double Word Program
200
10
s
Program/Erase Cycles (per Block)
100,000
cycles
Symbol
Parameter
Min
Max
Unit
tEHQ7V
Chip Enable High to DQ7 Valid (Program, E Controlled)
10
200
s
Chip Enable High to DQ7 Valid (Block Erase, E Controlled)
1.0
10
sec
tEHQV
Chip Enable High to Output Valid (Program)
10
200
s
Chip Enable High to Output Valid (Block Erase)
1.0
10
sec
tQ7VQV
Q7 Valid to Output Valid (Data Polling)
0
ns
tWHQ7V
Write Enable High to DQ7 Valid (Program, W Controlled)
10
200
s
Write Enable High to DQ7 Valid (Block Erase, W Controlled)
1.0
10
sec
tWHQV
Write Enable High to Output Valid (Program)
10
200
s
Write Enable High to Output Valid (Block Erase)
1.0
10
sec
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