參數(shù)資料
型號: M48T128V
廠商: 意法半導(dǎo)體
元件分類: SRAM
英文描述: 3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM
中文描述: 3.3 - 5V的1兆位的SRAM 128KB的x8計時器
文件頁數(shù): 20/22頁
文件大?。?/td> 340K
代理商: M48T128V
7/22
M48T128Y, M48T128V*
READ Mode
The M48T128Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Ad-
dress Inputs defines which one of the 131,072
bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within tAVQV (Address Access Time) after the last
address input signal is stable, providing the E and
G access times are also satisfied. If the E and G
access times are not met, valid data will be avail-
able after the latter of the Chip Enable Access
Times (tELQV) or Output Enable Access Time
(tGLQV). The state of the eight three-state Data I/O
signals is controlled by E and G. If the outputs are
activated before tAVQV, the data lines will be driven
to an indeterminate state until tAVQV. If the Ad-
dress Inputs are changed while E and G remain
active, output data will remain valid for tAXQX (Out-
put Data Hold Time) but will go indeterminate until
the next Address Access.
Figure 5. READ Mode AC Waveforms
Note: WE = High.
Table 3. READ Mode AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF.
Symbol
Parameter(1)
M48T128Y
M48T128V
Unit
–70
–85
Min
Max
Min
Max
tAVAV
READ Cycle Time
70
85
ns
tAVQV
Address Valid to Output Valid
70
85
ns
tELQV
Chip Enable Low to Output Valid
70
85
ns
tGLQV
Output Enable Low to Output Valid
40
55
ns
tELQX
(2)
Chip Enable Low to Output Transition
5
ns
tGLQX
(2)
Output Enable Low to Output Transition
5
ns
tEHQZ
(2)
Chip Enable High to Output Hi-Z
25
30
ns
tGHQZ
(2)
Output Enable High to Output Hi-Z
25
30
ns
tAXQX
Address Transition to Output Transition
10
5
ns
AI01197
tAVAV
tAVQV
tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
DATA OUT
A0-A16
E
G
DQ0-DQ7
VALID
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