參數(shù)資料
型號(hào): M48T12-70PC1
廠商: 意法半導(dǎo)體
英文描述: 16 Kbit 2Kb x8 TIMEKEEPER[ SRAM
中文描述: 16千位2KB的x8計(jì)時(shí)器[靜態(tài)存儲(chǔ)器
文件頁(yè)數(shù): 9/15頁(yè)
文件大小: 94K
代理商: M48T12-70PC1
AI01019
5V
OUT
CL = 100pF
CL includes JIG capacitance
1.8k
DEVICE
UNDER
TEST
1k
Figure 4. AC Testing Load Circuit
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0V to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Table 4. AC Measurement Conditions
AI01329
LITHIUM
CELL
OSCILLATOR AND
CLOCK CHAIN
VPFD
VCC
VSS
32,768 Hz
CRYSTAL
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
8 x 8 BiPORT
SRAM ARRAY
2040 x 8
SRAM ARRAY
A0-A10
DQ0-DQ7
E
W
G
POWER
BOK
Figure 3. Block Diagram
Byte 7F8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting.
The eight clock bytes are not the actual clock
counters themselves; they are memory locations
consisting of BiPORT
read/write memory cells.
The M48T02/12 includes a clock control circuit
which updates the clock bytes with current informa-
tion once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array.
The M48T02/12 also has its own Power-fail Detect
circuit. The control circuitry constantlymonitors the
single 5V supply for an out of tolerance condition.
When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system op-
eration brought on by low VCC.As VCC falls below
approximately3V, the control circuitry connectsthe
battery which maintains data and clock operation
until valid power returns.
3/15
M48T02, M48T12
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