![](http://datasheet.mmic.net.cn/90000/M44C090-XXX-FL16_datasheet_2360652/M44C090-XXX-FL16_103.png)
103
Atmel ATmega16/32/64/M1/C1 [DATASHEET]
7647K–AVR–12/13
An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn flag
according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for
updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a
low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value
written to OCRnA or ICRn is lower than the current value of TCNTn, the counter will miss the compare match. The counter will
then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In
many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCRnA for defining TOP
(WGMn3:0 = 15) since the OCRnA then will be double buffered.
For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical level on each compare match
by setting the compare output mode bits to toggle mode (COMnA1:0 = 1). The OCnA value will not be visible on the port pin
unless the data direction for the pin is set to output (DDR_OCnA = 1). The waveform generated will have a maximum frequency
of fOCnA = fclk_I/O/2 when OCRnA is set to zero (0x0000). The waveform frequency is defined by the following equation:
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the normal mode of operation, the TOVn flag is set in the same timer clock cycle that the counter counts from MAX to
0x0000.
13.8.3 Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform
generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from
BOTTOM to TOP then restarts from BOTTOM. In non-inverting compare output mode, the output compare (OCnx) is set on the
compare match between TCNTn and OCRnx, and cleared at TOP. In inverting compare output mode output is cleared on
compare match and set at TOP. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice
as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high frequency
makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows
physically small sized external components (coils, capacitors), hence reduces total system cost.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution
allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM
resolution in bits can be calculated by using the following equation:
In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or
0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 = 14), or the value in OCRnA (WGMn3:0 = 15). The counter is
then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in
Figure 13-7. The figure
shows fast PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a
histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small
horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx interrupt flag
will be set when a compare match occurs.
f
OCnA
f
clk_I/O
2 N
1
OCRnA
+
()
--------------------------------------------------
=
R
FPWM
TOP
1
+
()
log
2
()
log
----------------------------------
=