參數(shù)資料
型號: M40SZ100WMH
廠商: 意法半導體
英文描述: 5V or 3V NVRAM SUPERVISOR FOR LPSRAM
中文描述: 5V或3V的LPSRAM NVRAM中督導員
文件頁數(shù): 2/19頁
文件大?。?/td> 285K
代理商: M40SZ100WMH
M40SZ100Y, M40SZ100W
10/19
Figure 11. Power Up Timing
Table 6. Power Down/Up AC Characteristics
Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V or 4.5 to 5.5V(except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC
passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Symbol
Parameter(1)
Min
Max
Unit
tF
(2)
VPFD (max) to VPFD (min) VCC Fall Time
300
s
tFB
(3)
VPFD (min) to VSS VCC Fall Time
10
s
tPFD
PFI to PFO Propagation Delay
15
25
s
tR
VPFD(min) to VPFD (max) VCC Rise Time
10
s
tEPD
Chip Enable Propagation Delay (Low or High)
M40SZ100Y
10
ns
M40SZ100W
15
ns
tRB
VSS to VPFD (min) VCC Rise Time
1s
tCER
Chip Enable Recovery
40
120
ms
tREC
VPFD (max) to RST High
40
200
ms
tWPT
Write Protect Time
40
200
s
AI03937
VCC
E
ECON
tR
tCER
VOHB
VPFD (max)
VPFD (min)
VSO
VPFD
tEPD
RST
tREC
tRB
VALID
PFO
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