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參數(shù)資料
| 型號： | M40SZ100WMH |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 5V or 3V NVRAM SUPERVISOR FOR LPSRAM |
| 中文描述： | 5V或3V的LPSRAM NVRAM中督導(dǎo)員 |
| 文件頁數(shù)： | 18/19頁 |
| 文件大?。?/td> | 285K |
| 代理商： | M40SZ100WMH |
M40SZ100Y, M40SZ100W
8/19
OPERATION
The M40SZ100Y/W, as shown in Figure 7, page 5,
can control one (two, if placed in parallel) standard
low-power SRAM. This SRAM must be configured
to have the chip enable input disable all other input
signals. Most slow, low-power SRAMs are config-
ured like this, however many fast SRAMs are not.
During normal operating conditions, the condi-
tioned chip enable (ECON) output pin follows the
chip enable (E) input pin with timing shown in Ta-
VOUT. This switch has a voltage drop of less than
0.3V (IOUT1).
When VCC degrades during a power failure, ECON
is forced inactive independent of E. In this situa-
tion, the SRAM is unconditionally write protected
as VCC falls below an out-of-tolerance threshold
(VPFD). For the M40SZ100Y/W the power fail de-
If chip enable access is in progress during a power
fail detection, that memory cycle continues to com-
pletion before the memory is write protected. If the
memory cycle is not terminated within time tWPT,
ECON is unconditionally driven high, write protect-
ing the SRAM. A power failure during a WRITE cy-
cle may corrupt data at the currently addressed
location, but does not jeopardize the rest of the
SRAM's contents. At voltages below VPFD (min),
the user can be assured the memory will be write
protected within the Write Protect Time (tWPT) pro-
As VCC continues to degrade, the internal switch
disconnects VCC and connects the internal battery
to VOUT. This occurs at the switchover voltage
(VSO). Below the VSO, the battery provides a volt-
age VOHB to the SRAM and can supply current
When VCC rises above VSO, VOUT is switched
back to the supply voltage. Output ECON is held in-
active for tCER (120ms maximum) after the power
supply has reached VPFD, independent of the E in-
put, to allow for processor stabilization (see Figure
Data Retention Lifetime Calculation
Most low power SRAMs on the market today can
be used with the M40SZ100Y/W NVRAM Control-
ler. There are, however some criteria which should
be used in making the final choice of which SRAM
to use. The SRAM must be designed in a way
where the chip enable input disables all other in-
puts to the SRAM. This allows inputs to the
M40SZ100Y/W and SRAMs to be “Don't care”
page 9). The SRAM should also guarantee data
retention down to VCC = 2.0V. The chip enable ac-
cess time must be sufficient to meet the system
needs with the chip enable propagation delays in-
cluded.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion
current
specifications
for
the
particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use. The data retention current value of the
SRAMs can then be added to the ICCDR value of
the M40SZ100Y/W to determine the total current
requirements for data retention. The available bat-
tery capacity for the SNAPHAT of your choice
(see Table 13, page 17) can then be divided by
this current to determine the amount of data reten-
tion available.
CAUTION: Take care to avoid inadvertent dis-
charge through VOUT and ECON after battery has
been attached.
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
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| M40SZ100WMH6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V or 3V NVRAM SUPERVISOR FOR LPSRAM |
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| M40SZ100WMH6F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5 V or 3 V NVRAM supervisor for LPSRAM |
| M40SZ100WMH6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V or 3V NVRAM SUPERVISOR FOR LPSRAM |
| M40SZ100WMQ | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V or 3V NVRAM SUPERVISOR FOR LPSRAM |
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