參數(shù)資料
型號(hào)： M38851M3-XXXHP
廠商： Renesas Technology Corp.
英文描述： Dual 2.7-V High Slew Rate Rail-To-Rail Output Operational Amplifier 8-SOIC 0 to 70
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 85/103頁
文件大小： 1580K
代理商： M38851M3-XXXHP
3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
81
Fig. 77 Flash memory control registers
Fig. 78 CPU rewrite mode set/reset flowchart
Flash memory control register (address 0FFE16)
FMCR
RY/BY status flag (FMCR0)
0: Busy (being programmed or erased)
1: Ready
CPU reprogram mode select bit (FMCR1) (Note 2)
0: Normal mode (Software commands invalid)
1: CPU rewrite mode (Software commands acceptable)
CPU reprogram mode entry flag (FMCR2)
0: Normal mode
1: CPU rewrite mode
Flash memory reset bit (FMCR3) (Note 3)
0: Normal operation
1: Reset
User ROM area / Boot ROM area select bit (FMCR4) (Note 4)
0: User ROM area accessed
1: Boot ROM area accessed
Reserved bits (Indefinite at read/ “0” at write)
b0
b7
Notes1: The contents of flash memory control register are “XXX00001” just after reset release.
2: For this bit to be set to “1”, the user needs to write “0” and then “1” to it in succession. If it is not
this procedure, this bit will not be set to ”1”. Additionally, it is required to ensure that no interrupt
will be generated during that interval.
Use the control program in the area except the built-in flash memory for write to this bit.
3: This bit is valid when the CPU rewrite mode select bit is “1”. Set this bit 3 to “0” subsequently after
setting bit 3 to “1”.
4: Use the control program in the area except the built-in flash memory for write to this bit.
End
Start
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing “1” and then “0” in succession) (Note 2)
Single-chip mode, or boot mode
Set CPU mode register (Note 1)
Using software command execute erase,
program, or other operation
Jump to transferred control program in RAM
(Subsequent operations are executed by control
program in this RAM)
Transfer CPU reprogram mode
control program to internal RAM
Notes 1: Set bit 6,7 (Main clock division ratio selection bits ) at CPU mode register (003B16).
2: Before exiting the CPU reprogram mode after completing erase or program operation, always be sure to
execute a read array command or reset the flash memory.
Write “0” to CPU reprogram mode select bit
Set CPU reprogram mode select bit to “1” (by
writing “0” and then “1” in succession)(Note 3)
Check the CPU reprogram mode entry flag
*1
Program in ROM
Program in RAM
相關(guān)PDF資料
PDF描述
M38851M4-XXXHP Dual 2.7-V High Slew Rate Rail-To-Rail Output Operational Amplifier 8-MSOP 0 to 70
M38851M8-XXXHP Dual 2.7-V High Slew Rate Rail-To-Rail Output Operational Amplifier 8-MSOP 0 to 70
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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