參數(shù)資料
型號(hào)： M38851M3-XXXHP
廠商： Renesas Technology Corp.
英文描述： Dual 2.7-V High Slew Rate Rail-To-Rail Output Operational Amplifier 8-SOIC 0 to 70
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 34/103頁(yè)
文件大?。?/td> 1580K
代理商： M38851M3-XXXHP
35
3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Function
In conformity with Philips I2C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I2C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at
φ = 4 MHz)
Table 10 Multi-master I2C-BUS interface functions
Item
Format
Communication mode
System clock
φ = f(XIN)/2 (high-speed mode)
φ = f(XIN)/8 (middle-speed mode)
MULTI-MASTER I2C-BUS INTERFACE
The multi-master I2C-BUS interface is a serial communications cir-
cuit, conforming to the Philips I2C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
Figure 31 shows a block diagram of the multi-master I2C-BUS in-
terface and Table 10 lists the multi-master I2C-BUS interface
functions.
This multi-master I2C-BUS interface consists of the I2C address
register, the I2C data shift register, the I2C clock control register,
the I2C control register, the I2C status register, the I2C start/stop
condition control register and other control circuits.
When using the multi-master I2C-BUS interface, set 1 MHz or
more to system clock
φ.
Fig. 31 Block diagram of multi-master I2C-BUS interface
: Purchase of MITSUBISHI ELECTRIC CORPORATIONS I2C components conveys a license under the Philips I2C Patent Rights to use these components
an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
SCL clock frequency
I2C address register
b7
b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0
RWB
Noise
elimination
circuit
Serial data
(SDA)
Address comparator
b7
I2C data shift register
b0
Data
control
circuit
System clock (
φ)
Interrupt
generating
circuit
Interrupt request signal
(I2CIRQ)
b7
MST TRX BB
PIN
AL AAS AD0 LRB
b0
S1
b7
b0
TISS
10BIT
SAD
ALS
BC2 BC1
BC0
S1D
Bit counter
BB
circuit
Clock
control
circuit
Noise
elimination
circuit
Serial
clock
(SCL)
b7
b0
ACK
BIT
FAST
MODE
CCR4 CCR3 CCR2 CCR1 CCR0
Internal data bus
Clock division
S0
S2
S0D
AL
circuit
ES0
SIS
I2C start/stop condition
control register
SIP SSC4SSC3 SSC2 SSC1 SSC0
I2C clock control register
I2C status register
S2D
Interrupt
generating
circuit
Interrupt request signal
(SCLSDAIRQ)
Stop selection
STSP
SEL
CLK
STP
I2C clock control register
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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