參數資料
型號: M38851M1-XXXHP
廠商: Renesas Technology Corp.
英文描述: Single 2.7-V High-Slew-Rate Rail-to-Rail Output Operational Amplifier With Shutdown 8-SOIC -40 to 125
中文描述: 單芯片8位CMOS微機
文件頁數: 62/103頁
文件大小: 1580K
代理商: M38851M1-XXXHP
3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
60
Operation of Serialized IRQ
A cycle operation of serialized IRQ starts with Start Frame and fin-
ishes with Stop Frame. There are two modes of operation :
Continuous (Idle) mode and Quiet (Active) mode. The next opera-
tion mode is determined by monitoring the stop frame pulse width.
qTiming of serialized IRQ cycle
Figure 54 shows the timing diagram of serialized IRQ cycle.
(1) Start Frame
The Start Frame is detected when the SERIRQ line remains “L” in
4 to 8 clocks.
Fig. 54 Timing diagram of serialized IRQ cycle
(2) IRQ/Data Frame
Each IRQ/Data Frame is three clocks. When the IRQi (i = 0, 1, x)
request is “0”, then the SERIRQ line is driven to “L” during the
Sample phase (1st clock) of the corresponding IRQ/Data frame,
to “H” during the Recovery phase (2nd clock), to tri-state during
the Turn-around phase (3rd clock). When the IRQi request is “1”,
then the SERIRQ line is tri-state in all phases (3 clocks period).
(3) Stop Frame
The Stop Frame is detected when the SERIRQ line remains “L” in
2 or 3 clocks. The next operation mode is Quiet mode when the
pulse width of “L” is 2 clocks. The next operation mode is the
Continuous mode when the pulse width is 3 clocks.
Start frame
IRQ0 frame
IRQ1 frame
IRQ15 frame
IOCHK frame
IRQ1
device
control
Stop frame
To the next cycle
IRQ15
device
control
Host control
Clock
SERIRQ
Driver source
Host control
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相關代理商/技術參數
參數描述
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