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3850 Group (Spec. H) User’s Manual
3-39
APPENDIX
3.3 Notes on use
3.3.12 Notes on CPU rewrite mode of flash memory version
(1)
Operation speed
During CPU rewrite mode, set the internal clock frequency 4MHz or less by using the main clock
division ratio selection bits (bits 6, 7 at address 003B16).
(2)
Instructions inhibited against use
The instructions which refer to the internal data of the flash memory cannot be used during CPU
rewrite mode .
(3)
Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode because they refer to the internal data of
the flash memory.
(4)
Watchdog timer
In case of the watchdog timer has been running already, the internal reset generated by watchdog
timer underflow does not happen, because of watchdog timer is always clearing during program or
erase operation.
(5)
Reset
Reset is always valid. In case of CNVSS = “H” when reset is released, boot mode is active. So the
program starts from the address contained in addresses FFFC16 and FFFD16 in boot ROM area.
3.3.13 Notes on restarting oscillation
sRestarting oscillation
Usually, when the MCU stops the clock oscillation by STP instruction and the STP instruction has
been released by an external interrupt source, the fixed values of Timer 1 and Prescaler 12 (Timer
1 = “0116”, Prescaler 12 = “FF16”) are automatically reloaded in order for the oscillation to stabilize.
The user can inhibit the automatic setting by writing “1” to bit 0 of MISRG (address 003816).
However, by setting this bit to “1”, the previous values, set just before the STP instruction was
executed, will remain in Timer 1 and Prescaler 12. Therefore, you will need to set an appropriate
value to each register, in accordance with the oscillation stabilizing time, before executing the STP
instruction.
q Reason
Oscillation will restart when an external interrupt is received. However, internal clock
φ is supplied
to the CPU only when Timer 1 starts to underflow. This ensures time for the clock oscillation using
the ceramic resonators to be stabilized.