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| 型號： | M38254M6-337FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 29/70頁 |
| 文件大?。?/td> | 607K |
| 代理商： | M38254M6-337FP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
29
A-D CONVERTER
The functional blocks of the A-D converter are described below.
[A-D Conversion Register (AD)] 0035
16
The A-D conversion register is a read-only register that contains
the result of an A-D conversion. When reading this register during
an A-D conversion, the previous conversion result is read.
[A-D Control Register (ADCON)] 0034
16
The A-D control register controls the A-D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 signals
the completion of an A-D conversion. The value of this bit remains
at “0” during an A-D conversion, then changes to “1” when the A-
D conversion is completed. Writing “0” to this bit starts the A-D
conversion. Bit 4 controls the transistor which breaks the through
current of the resistor ladder. When bit 5, which is the AD external
trigger valid bit, is set to “1”, this bit enables A-D conversion even
by a falling edge of an ADT input. Set ports which share with ADT
pins to input when using an A-D external trigger.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AV
SS
and V
REF
by 256, and outputs the divided voltages.
Channel Selector
The channel selector selects one of the input ports P6
7
/AN
7
–P6
0
/
AN
0
.
Comparator and Control Circuit
The comparator and control circuit compare an analog input volt-
age with the comparison voltage and store the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
set f(X
IN
) to at least 500kHz during A-D conversion.
Use the clock divided from the main clock X
IN
as the internal clock
φ
.
Fig. 27 A-D converter block diagram
Fig. 26 Structure of A-D control register
A-D control register
(ADCON : address 0034
16
)
Analog input pin selection bits
0 0 0 : P6
0
/AN
0
0 0 1 : P6
1
/AN
1
0 1 0 : P6
2
/AN
2
0 1 1 : P6
3
/AN
3
1 0 0 : P6
4
/AN
4
1 0 1 : P6
5
/AN
5
1 1 0 : P6
6
/AN
6
1 1 1 : P6
7
/AN
7
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
V
REF
input switch bit
0 : OFF
1 : ON
AD external trigger valid bit
0 : A-D external trigger invalid
1 : A-D external trigger valid
Interrupt source selection bit
0 : Interrupt request at A-D
conversion completed
1 : Interrupt request at ADT
input falling
Not used (returns “0” when read)
b7
b0
Comparator
A-D control circuit
ADT/A-D interrupt request
AV
SS
V
REF
P6
0
/AN
0
P6
1
/AN
1
Data bus
A-D control register
b7
b0
A-D conversion
register
8
Resistor ladder
C
P6
7
/AN
7
P6
6
/AN
6
P6
5
/AN
5
P6
4
/AN
4
P6
3
/AN
3
P6
2
/AN
2
P5
7
/ADT
3
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