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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3825 Group
15
Table 6. I/O ports functions
Related SFRs
PULL register A
Segment output enable
register
PULL register A
Segment output enable
register
Port P1 output
control register
PULL register A
PULL register A
Interrupt control register 2
PULL register A
Segment output enable
register
Clock output control
register
PULL register A
PULL register A
Interrupt edge selection
register
PULL register A
Serial I/O control register
Serial I/O status register
UART control register
PULL register B
Interrupt edge selection
register
PULL register B
Timer X mode register
PULL register B
Timer X mode register
PULL register B
Timer Y mode register
PULL register B
Timer 123 mode register
PULL register B
A-D control register
PULL register B
A-D control register
PULL register B
PULL register A
CPU mode register
LCD mode register
Input/Output
Output
Output
Input/output,
individual bits
Input/output,
individual bits
Output
Input/output,
individual bits
Input/output,
individual bits
Input/output,
individual bits
Input
Input/output,
individual bits
Input/output,
individual bits
Output
Output
Name
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
Port P8
Common
Segment
Pin
P0
0
/SEG
26
–
P0
7
/SEG
33
P1
0
/SEG
34
–
P1
5
/SEG
39
P1
6
, P1
7
P2
0
–P2
7
P3
0
/SEG
18
–
P3
7
/SEG
25
P4
0
/f(X
IN
)/
f(X
IN
)/2,
P4
1
/f(X
IN
)/5/
f(X
IN
)/10
P4
2
/INT
0
,
P4
3
/INT
1
P4
4
/R
X
D
P54/T
X
D
P4
6
/S
CLK
P4
7
/S
RDY
P5
0
/INT
2
,
P5
1
/INT
3
P5
2
/RTP
0
,
P5
3
/RTP
1
P5
4
/CNTR
0
P5
5
/CNTR
1
P5
6
/T
OUT
P5
7
/ADT
P6
0
/AN
0
–
P6
7
/AN
7
P7
0
P7
1
–P7
7
P8
0
/X
COUT
P8
1
/X
CIN
COM
0
–COM
3
SEG
0
–SEG
17
Non-Port Function
LCD segment output
LCD segment output
Key-on wake up
interrupt input
LCD segment output
Clock output
External interrupt input
Serial I/O function I/O
External interrupt input
Real time port
function output
Timer X function I/O
Timer Y function input
Timer 2 output
A-D trigger input
A-D conversion input
Sub-clock
generating circuit
I/O Format
CMOS 3-state output
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
LCD common output
LCD segment output
Diagram No.
(1)
(1)
(2)
(2)
(1)
(2)
(3)
(4)
(5)
(6)
(2)
(7)
(8)
(9)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
Note 1:
When using double-function ports as functional I/O pins, refer the method to the relevant sections.
2:
Make sure that the input level at each pin is either 0 V or V
CC
during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from V
CC
to V
SS
through the input-stage gate.