參數(shù)資料
型號： M38235G3-XXXFP
廠商： Renesas Technology Corp.
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 54/76頁
文件大?。?/td> 896K
代理商： M38235G3-XXXFP
Rev.2.02 Jun 19, 2007 page 54 of 73
REJ03B0146-0202
3823 Group
Notes 1 :
Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2 :
The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended.
3 :
Timer and LCD operate in the wait mode.
4 :
When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in frequency/2/4/8 mode.
5 :
When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode.
6 :
Wait until oscillation stabilizes after oscillating the main clock X
IN
before the switching from the low-speed mode to frequency/2/4/8 mode.
7 :
The example assumes that 8 MHz is being applied to the X
IN
pin and 32 kHz to the X
CIN
pin.
indicates the internal clock.
8 :
f(SUB) is the source oscillation frequency in low-speed mode. f(SUB) shows the oscillation frequency of X
CIN
or the on-chip oscillator.
Internal clock
is f(SUB)/2 in the low-speed mode.
9 :
Set the CPU mode expansion register in advance when switching to low-speed mode which uses mode divided by 4 and on-chip oscillator.
10:
In low speed mode, the system clock
can be switched to the on-chip oscillator or X
CIN
. Use the on-chip oscillator control bit (bit 0 in the CPU mode
expansion register) for settings. To set this bit to "0" from "1", wait until X
CIN
oscillation stabilizes.
CM
4
: Port Xc switch bit
(Note 1)
0: I/O port (Oscillation stopped)
1: X
CIN
, X
COUT
oscillating function
CM
5
: Main clock (X
IN
–X
OUT
) stop bit
(Note 2)
0: Oscillating
1: Stopped
CM
6
: Main clock division ratio selection bit
0: f(X
IN
)/2 (frequency/2 mode),
or f(X
IN
)/4 (frequency/4 mode)
(Note 3)
1: f(X
IN
)/8 (frequency/8 mode)
CM
7
: Internal system clock selection bit
0: X
IN
–X
OUT
selected (frequency/2/4/8 mode)
1: X
CIN
–X
COUT
, or on-chip oscillator selected
(low-speed mode)
(Note 4)
CPU mode register
(CPUM : address 003B
16
)
b7
b4
Rese
t
CM
6
“1”
“0”
C
4
“
“
CM
7
CM
6
CM
5
CM
4
= 0 (8 MHz selected)
Frequency/8 mode (f(
φ
) = 1 MHz)
Frequency/8 mode (f(
φ
) = 1 MHz)
CM
7
CM
6
CM
5
CM
4
= 0 (8 MHz selected)
φ
)) = 2 MHz)
Frequency/2 mode (f(
φ
φ
)) = 2 MHz)
Frequency/2 mode (f(
φ
7
6
5
CM
4
= 0 or EXPCM0 = 1
(On-chip oscillator oscillation)
7
= 1 (32 kHz or on-chip
CM
CM
6
CM
5
CM
4
= 1 (Middle-speed)
Low-speed mode (f(SUB)/2)
7
= 1 (32 kHz or on-chip
CM
CM
6
CM
5
CM
4
= 0 (High-speed)
Low-speed mode (f(SUB)/2)
7
= 1 (32 kHz or on-chip
CM
CM
6
CM
5
CM
4
= 1 (Middle-speed)
Low-power dissipation mode
CM
6
“1”
“0”
CM
6
“1”
“0”
CM
6
“1”
“0”
C
4
“
“
C
7
“
“
C
7
“
“
C
5
“
“
C
5
“
“
CM
4
“1
CM
6
“1
“0
“0
CM
4
CM
6
“0
“1
“1
“0
CM
5
“1
CM
6
“1
“0
“0
CM
5
CM
6
“0
“1
“1
“0
CM
7
CM
6
CM
5
CM
4
= 0 or EXPCM0 = 1
(On-chip oscillator oscillation)
7
= 1 (32 kHz or on-chip
CM
CM
6
CM
5
CM
4
= 0 (high-speed)
Low-power dissipation mode
On-chip oscillator control bit
0 : On-chip oscillator not used
(on-chip oscillator stopping)
1 : On-chip oscillator used
(Note 1)
(on-chip oscillator oscillating)
Frequency/4 mode control bit
(Note 2)
(Valid only when high-speed mode)
0 : Frequency/2 mode
φ
= f(X
IN
)/2
1 : Frequency/4 mode
φ
= f(X
IN
)/4
Not used (returns “0” when read)
(Do not write “1” to this bit)
CPU mode extension register
(EXPCM : address: 002B
16
,)
b7
b4
Note 1 :
The on-chip oscillator is selected for the operation clock
in low-speed mode regardless of X
CIN-
X
COUT
.
2 :
Valid only when the main clock division ratio selection bit
(bit 6 in the CPU mode register) is set to "0".
When "1" (frequency/8 mode) is selected for the main clock
division ratio selection bit or when the internal system clock
selection bit is set to 1, set "0" to the frequency/4 mode control bit.
Note 1 :
In low speed mode (X
CIN
is selected as the system clock
X
CIN
-X
COUT
oscillation does not stop even if the port X
C
switch bit
is set to "0".
2 :
In frequency/2/4/8 mode, X
IN
-X
OUT
oscillation does not stop even if
the main clock (X
IN
-X
OUT
) stop bit is set to "1".
3 : When the system clock
is divided by 4 of f(X
IN
), set the bit 6 in
the CPU mode register to “0” after setting the bit 1 in the CPU
mode extension register to “1”.
4 : When using the on-chip oscillator in low-speed mode, set the bit 7
in the CPU mode register to “1” after setting the bit 0 in the CPU
mode extension register to “1”.
),
Fig. 57 State transitions of system clock
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