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參數(shù)資料
| 型號： | M381L3223EUM-CCC |
| 元件分類： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM MODULE, 0.65 ns, DMA184 |
| 封裝： | ROHS COMPLIANT, DIMM-184 |
| 文件頁數(shù)： | 17/22頁 |
| 文件大小： | 402K |
| 代理商： | M381L3223EUM-CCC |
DDR SDRAM
256MB, 512MB Unbuffered DIMM
Rev. 1.2 July 2005
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Speed @CL2
-
133MHz
Speed @CL2.5
166MHz
Speed @CL3
200MHz
-
CL-tRCD-tRP
3-3-3
2.5-3-3
184Pin Unbuffered DIMM based on 256Mb E-die (x8, x16)
VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333
VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency : DDR333(2.5 Clock), DDR400(3 Clock)
Programmable Burst length (2, 4, 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
Serial presence detect with EEPROM
PCB : Height 1,250 (mil) & single (256, 512MB), double (1GB) sided
SSTL_2 Interface
66pin TSOP II Leaded & Pb-Free(RoHS compliant) package
1.0 Ordering Information
2.0 Operating Frequencies
Note : Leaded and Lead-free(Pb-free) can be discriminated by PKG P/N (T : 66 TSOP with Leaded, U : 66 TSOP with Lead-free)
Part Number
Density
Organization
Component Composition
Height
M368L3223ET(U)M-C(L)CC
256MB
32M x 64
32Mx8 (K4H560838E) * 8EA
1,250mil
M368L3223ET(U)N-C(L)B3
M381L3223ET(U)M-C(L)CC/B3
32M x 72
32Mx8 (K4H560838E) * 9EA
1,250mil
M368L6423ET(U)M-C(L)CC
512MB
64M x 64
32Mx8 (K4H560838E) * 16EA
1,250mil
M368L6423ET(U)N-C(L)B3
M381L6423ET(U)M-C(L)CC/B3
64M x 72
32Mx8 (K4H560838E) * 18EA
1,250mil
3.0 Feature
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相關代理商/技術參數(shù) |
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|---|---|
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