參數(shù)資料
型號： M38039FFSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, 1.78 MM PITCH, SHRINK, PLASTIC, DIP-64
文件頁數(shù)： 48/138頁
文件大小： 1887K
代理商： M38039FFSP
Rev.4.01
Nov 14, 2003
page 15 of 136
3803/3804 Group
MISRG
(1) Bit 0 of address 001016: Oscillation stabilizing time set af-
ter STP instruction released bit
When the MCU stops the clock oscillation by the STP instruction
and the STP instruction has been released by an external interrupt
source, usually, the fixed values of Timer 1 and Prescaler 12
(Timer 1 = 0116, Prescaler 12 = FF16) are automatically reloaded
in order for the oscillation to stabilize. The user can inhibit the au-
tomatic setting by setting “1” to bit 0 of MISRG (address 001016).
However, by setting this bit to “1”, the previous values, set just be-
fore the STP instruction was executed, will remain in Timer 1 and
Prescaler 12. Therefore, you will need to set an appropriate value
to each register, in accordance with the oscillation stabilizing time,
before executing the STP instruction.
Figure 12 shows the structure of MISRG.
(2) Bits 1, 2, 3 of address 001016: Middle-speed Mode Auto-
matic Switch Function
In order to switch the clock mode of an MCU which has a sub-
clock, the following procedure is necessary:
set CPU mode register (003B16) --> start main clock oscillation -->
wait for oscillation stabilization --> switch to middle-speed mode
(or high-speed mode).
However, the 3803/3804 group has the built-in function which au-
tomatically switches from low to middle-speed mode either by the
SCL/SDA interrupt (only for the 3804 group) or by program.
qMiddle-speed mode automatic switch by SCL/SDA Interrupt
(only for 3804 group)
The SCL/SDA interrupt source enables an automatic switch when
the middle-speed mode automatic switch set bit (bit 1) of MISRG
(address 001016) is set to “1”. The conditions for an automatic
switch execution depend on the settings of bits 5 and 6 of the I2C
start/stop condition control register (address 001616). Bit 5 is the
SCL/SDA interrupt pin polarity selection bit and bit 6 is the SCL/
SDA interrupt pin selection bit. The main clock oscillation stabiliz-
ing time can also be selected by middle-speed mode automatic
switch wait time set bit (bit 2) of the MISRG.
qMiddle-speed mode automatic switch by program
The middle-speed mode can also be automatically switched by
program while operating in low-speed mode. By setting the
middle-speed automatic switch start bit (bit 3) of MISRG (address
001016) to “1” in the condition that the middle-speed mode auto-
matic switch set bit is “1” while operating in low-speed mode, the
MCU will automatically switch to middle-speed mode. In this case,
the oscillation stabilizing time of the main clock can be selected by
the middle-speed automatic switch wait time set bit (bit 2) of
MISRG (address 001016).
Fig.12 Structure of MISRG
MISRG
(MISRG : address 001016)
Oscillation stabilizing time set after STP instruction
released bit
Middle-speed mode automatic switch set bit
Middle-speed mode automatic switch wait time set bit
Middle-speed mode automatic switch start bit
(Depending on program)
Not used (return “0” when read)
(Do not write “1” to this bit)
b7
b0
0: Automatically set “0116” to Timer 1,
“FF16” to Prescaler 12
1: Automatically set disabled
0: Not set automatically
1: Automatic switching enabled (Notes 1, 2)
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
0: Invalid
1: Automatic switch start (Note 2)
Notes1: During operation in low-speed mode, it is possible automatically to
switch to middle-speed mode owing to SCL/SDA interrupt. This is
valid only for the 3804 group.
2: When automatic switch to middle-speed mode from low-speed mode
occurs, the values of CPU mode register (3B16) change.
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