參數(shù)資料
型號： M38039FFSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PDIP64
封裝： 0.750 INCH, 1.78 MM PITCH, SHRINK, PLASTIC, DIP-64
文件頁數(shù)： 39/138頁
文件大小： 1887K
代理商： M38039FFSP
REVISION HISTORY
3803/3804 GROUP DATA SHEET
Rev.
Date
Description
Page
Summary
(1/5)
0.1
03/15/99
First Edition; Only including overview
The issue including all information will be released in April.
All pages
9
10
34
52
60
63
66
67
68
69
75
76
77
82
86
117
1.0
05/25/99
Functional descriptions are added.
2.0
09/09/99
“PRELIMINARY Notice: This is...” eliminated.
Product names are added into Figure 8.
Product names are added into Table 3.
Explanation of “Timer divider” of “8-bit Timers” is revised.
Explanation of Note 7 is revised.
Explanation of “A-D CONVERTER” is revised.
Explanations of Figure 56 are partly revised.
Explanations of “Watchdog Timer Initial Value” and “Watchdog Timer Operations”
are revised.
Explanations of Figure 60 are partly revised.
Explanation of “MULTI-MASTER I2C-BUS INTERFACE” is revised.
Explanation of Note eliminated.
Explanations of Figure 62 are partly revised.
Explanations of “I2C Data Shift Register” and “I2C Address Registers 0 to 2” are
revised.
Explanation of Bit 5 of “I2C Clock Control Register” is revised.
Value of “Setup time” and “Hold time” into Table 13 are revised.
Explanation of Bit 5 of “I2C Special Mode Status Register” is added.
Note is added into Figure 73.
Explanation of Bit 1 of “I2C Special Mode Control Register” is added.
Explanation of Bit 6 of “I2C Special Mode Control Register” is revised.
Note is added into Figure 74.
Register Contents of (21) into Figure 78 is revised.
Explanations of Figure 82 are partly revised.
Note 2 into Figure 82 is revised.
Table 28 is revised for only flash memory version.
Table 29 is added.
3.0
06/28/00
1
9
11-13
14
“qMinimum instruction execution time” of “FEATURES” is revised.
“qMemory size” of “FEATURES” is revised.
“<Flash memory mode>” of “FEATURES” is revised.
“sNotes” of “FEATURES” is revised.
Figure 8 is partly revised.
Explanations of “CENTRAL PROCESSING UNIT (CPU)” are added.
Explanation of bit 3 of “CPU mode register” is revised.
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