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參數(shù)資料
| 型號： | M38037M8H-XXXWG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PBGA64 |
| 封裝： | 6 X 6 MM, 0.65 MM PITCH, PLASTIC, FLGA-64 |
| 文件頁數(shù)： | 30/111頁 |
| 文件大?。?/td> | 1205K |
| 代理商： | M38037M8H-XXXWG |
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Rev.3.02
Nov 05, 2004
page 25 of 108
3803 Group (Spec. H)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
INTERRUPTS
The 3803 group (Spaec. H)’s interrupts are a type of vector and
occur by 16 sources among 21 sources: eight external, twelve in-
ternal, and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The reset and the BRK instruction cannot be disabled with any
flag or bit. The I (interrupt disable) flag disables all interrupts ex-
cept the reset and the BRK instruction interrupt.
When several interrupt requests occur at the same time, the inter-
rupts are received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt Source Selection
Which of each combination of the following interrupt sources can
be selected by the interrupt source selection register (address
003916).
1. INT0 or Timer Z
2. CNTR1 or Serial I/O3 reception
3. Serial I/O2 or Timer Z
7. INT4 or CNTR2
8. A-D converter or serial I/O3 transmission
External Interrupt Pin Selection
The occurrence sources of the external interrupt INT0 and INT4
can be selected from either input from INT00 and INT40 pin, or in-
put from INT01 and INT41 pin by the INT0, INT4 interrupt switch bit
of interrupt edge selection register (bit 6 of address 003A16).
s Notes
When setting the followings, the interrupt request bit may be set to
“1”.
When setting external interrupt active edge
Related register: Interrupt edge selection register (address 003A16)
Timer XY mode register (address 002316)
Timer Z mode register (address 002A16)
When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt source selection register
(address 003916)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to “0” (disabled).
Set the interrupt edge select bit or the interrupt source select bit
to “1”.
Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
{Set the corresponding interrupt enable bit to “1” (enabled).
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