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參數(shù)資料
| 型號： | M37906M8C-XXXSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42 |
| 文件頁數(shù)： | 35/99頁 |
| 文件大?。?/td> | 1313K |
| 代理商： | M37906M8C-XXXSP |
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63
8168C-MCU Wireless-02/10
AT86RF212
If AACK_FLTR_RES_FT = 0, the received reserved frame is only checked for a valid
FCS.
Bit 4 – AACK_UPLD_RES_FT
If AACK_UPLD_RES_FT = 1, received frames marked as reserved frames are further
processed. For these frames, interrupt IRQ_3 (TRX_END) is generated if the FCS is
valid.
In conjunction with the configuration bit AACK_FLTR_RES_FT = 1, these frames are
handled like IEEE 802.15.4 compliant data frames during RX_AACK transaction.
Otherwise, if AACK_UPLD_RES_FT = 0, frames with a reserved frame type are
blocked.
Bit 3 – Reserved
Bit 2 – AACK_ACK_TIME
According to IEEE 802.15.4-2006, section 7.5.6.4.2, the transmission of an
acknowledgment frame shall commence 12 symbol periods (aTurnaroundTime) after
the reception of the last symbol of a data or MAC command frame. This is achieved
with the reset value of the register bit AACK_ACK_TIME.
Alternatively, if AACK_ACK_TIME = 1, the acknowledgment response time is reduced
according to Table 5-24.
Table 5-24. Short ACK Response Time (AACK_ACK_TIME = 1)
PHY Mode
ACK response time [symbol periods]
BPSK-20, OQPSK-{100,200,400}
2
BPSK-40, OQPSK-{250,500,1000}
3
The reduced ACK response time is particularly useful for the High Data Rate Modes,
refer to section 7.1.4.
Bit 1 – AACK_PROM_MODE
Register bit AACK_PROM_MODE enables the promiscuous mode within the RX_AACK
mode; refer to IEEE 802.15.4-2006, section 7.5.6.5.
If this bit is set, incoming frames with a valid PHR generate interrupt IRQ_3
(TRX_END), even if the third level filter rules do not match or the FCS is not valid.
However, register bit RX_CRC_VALID (register 0x06) is set accordingly.
If a frame passes the third level filter rules, an acknowledgement frame is generated
and transmitted unless disabled by register bit AACK_DIS_ACK (register 0x2E,
CSMA_SEED_1).
Bit 0 – Reserved
Register 0x2C (XAH_CTRL_0):
Register 0x2C (XAH_CTRL_0) is a control register for Extended Operating Mode.
Table 5-25. Register 0x2C (XAH_CTRL_0)
Bit
7
6
5
4
Name
MAX_FRAME_RETRIES[3:0]
Read/Write
R/W
Reset Value
0
1
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