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83
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 95 Bit configuration of particular function select register 0
Fig. 94 Bit configuration of clock control register 0
7
0
6
5
0
4
0
3
2
1
0
Particular function select register 0
External clock input select bit
(Note)
0: Oscillation circuit is active. (The oscillator is connected.)
Watchdog timer is used at stop mode termination.
1: Oscillation circuit is inactive. (The externally-generated clock is input.)
When the system clock select bit =
“
0
”
,
watchdog timer is not used at stop mode termination.
When the system clock select bit =
“
1
”
,
watchdog timer is used at stop mode termination.
Fix this bit to
“
0
”
.
STP instruction invalidity select bit
(Note)
0: STP instruction is valid.
1: STP instruction is invalid.
Note:
Address
62
16
Writing to these bits requires the following procedure:
Write
“
55
16
”
to this register. (The bit status does not change only by this writing.)
Succeedingly, write
“
0
”
or
“
1
”
to each bit.
Also, use the
MOVM (MOVMB)
instruction or
STA (STAB, STAD)
instruction
7
6
5
4
1
3
2
1
0
1
Clock control register 0
Fix this bit to
“
1
”
.
PLL circuit operation enable bit
(Note 1)
0: PLL frequency multiplier is inactive, and pin V
CONT
is invalid (floating state).
1: PLL frequency multiplier is active, and pin V
CONT
is valid.
PLL multiplication ratio select bits
(Note 2)
00: Do not select.
01: Double
10: Triple
11: Quadruple
Fix this bit to
“
1
”
.
System clock select bit
(Note 3)
0: fX
IN
1: f
PLL
Peripheral device
’
s clock select bits 1, 0
See Table 10.
Address
BC
16
Notes 1:
When not using the PLL frequency multiplier, be sure to clear this bit to
“
0
”
.
In the stop mode, the PLL circuit is inactive regardless of this bit
’
s content; at this time, pin
V
CONT
is invalid.
2:
When rewriting this bit, be sure to clear bit 5 to
“
0
”
simultaneously. Also, after this bit is
rewritten, insert a waiting time of 2 ms, and then set bit 5 to
“
1
”
.
3:
When the PLL circuit operation enable bit (bit 1) has been cleared to
“
0
”
, this bit will also be
cleared to
“
0
”
. When bit 1 =
“
0
”
, nothing can be written to this bit. (Fixed to be
“
0
”
.)