參數(shù)資料
型號: M37905M4C
廠商: Mitsubishi Electric Corporation
英文描述: DIODE SCHOTTKY DUAL COMMON-ANODE 25V 200mW 0.32V-vf 200mA-IFM 1mA-IF 2uA-IR SOT-323 3K/REEL
中文描述: 16位CMOS微機(jī)
文件頁數(shù): 47/102頁
文件大小: 881K
代理商: M37905M4C
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
47
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Pulse mode 1
This mode divides a pules output port into 6 bits and 2bits and indi-
vidually control them.
When setting the pulse output mode select bit to
1
, and setting bits
2 and 1 to
0
and bit 0 to
1
of the waveform output select bits, the
following become the pulse output ports:
Six of RTP1
1
, RTP1
0
, RTP0
3
, RTP0
2
, RTP0
1
, RTP0
0
When setting the pulse output mode select bit to
1
, and setting bits
2 and 0 to
0
and bit 1 to
1
of the waveform output select bits, two
of RTP1
3,
RTP1
2
become the pulse output ports.
When setting the pulse output mode select bit to
1
, and setting bit 2
to
0
and bits 1 and 0 to
1
of the waveform output select bits, the
following two groups become the pulse output ports:
Two of RTP1
3
, RTP1
2
Six of RTP1
1
, RTP1
0
, RTP0
3
, RTP0
2
, RTP0
1
, RTP0
0.
Each time the contents of timer A3 counter become 0000
16,
the con-
tents of three-phase output data register 1 (address A9
16
)
s bits 7
and 6, which corresponding to RTP1
3
and RTP1
2
, are output from
ports.
Each time the contents of timer A0 counter become 0000
16,
the con-
tents of three-phase output data register 0 (address A8
16
)s
low or-
der 6 bits (bits 5 to 0), which corresponding to RTP1
1
, RTP1
0
,
RTP0
3,
RTP0
2,
RTP0
1,
RTP0
0,
are output from ports.
Whether to control these pulse output ports by an underflow of timer
A0 or an input edge to pin RTP
TRG0
is selected by the pulse output
trigger select bits of the three-phase output data register 0 (bits 7 and
6 at address A8
16
).
Additionally, pulse width modulation can be applied to RTP1
1,
RTP1
0,
RTP0
3,
RTP0
2,
RTP0
1,
and RTP0
0
. The pulse width modula-
tion timer select bits of the waveform output mode register (bits 5 and
4 at address A6
16
) select the type of pulse width modulation from the
following:
(1) When the pulse width modulation timer select bits =
00
, the
common modulation to six of RTP1
1
, RTP1
0
, RTP0
3
, RTP0
2
,
RTP0
1
, RTP0
0
is selected. For this modulation, since timer A1 is
necessary, be sure to actuate this timer in the pulse width modu-
lation mode.
(2) When the pulse width modulation timer select bits =
01
, the
modulation to the following two groups is selected; one consists
of RTP1
1
, RTP1
0
, RTP0
3
, and the other consists of RTP0
2
,
RTP0
1
, RTP0
0
. For this modulation, since timers A1 and A2 are
necessary, be sure to actuate these timers in the pulse width
modulation mode.
(3) When the pulse width modulation timer select bits =
10
, the
modulation to the following three groups is selected; one consists
of RTP1
1
, RTP1
0
, and another consists of RTP0
3
, RTP0
2
,
and the other consists of RTP0
1
, RTP0
0
. For this modulation,
since timers A1, A2, and A4 are necessary, be sure to actuate
these timers in the pulse width modulation mode.
Additionally, at this time, be sure to set the corresponding pulse
width modulation enable bit of the three-phase output data register 1
(bits 2 through 0 at address A9
16
) to
1
in order to enable the pulse
width modulation.
The other operations are the same as that of pulse mode 0. Figure
53 shows example waveforms in pulse mode 1.
In ports selecting pulse mode 1, output of RTP1
3
and RTP1
2
is con-
trolled by the waveform output control bit 0 (bit 6) of the waveform
output mode register; output of RTP1
1,
RTP1
0
, RTP0
3
, RTP0
2
,
RTP0
1
and RTP0
0
is done by the waveform output control bit 1 (bit
7).
When setting the waveform output control bit to
1
, waveform is out-
put from the corresponding port. When clearing that bit to
0
, wave-
form output from the corresponding port stops, and the port
becomes floating. These waveform output control bits 0, 1 are
cleared to
0
by reset, by inputting a falling edge to pin P6OUT
CUT
,
or by executing instructions.
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