參數(shù)資料
型號： M37736MHB
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機
文件頁數(shù)： 53/96頁
文件大小： 1328K
代理商： M37736MHB
53
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port P2 has two functions depending on the level of the BYTE pin. In
both cases, the I/O port function is lost.
When the BYTE pin level is “L”, port P2 functions as an address
output pin while
E
is “H” and as an even address data I/O pin while
E
is “L”. However, if an internal memory is read, external data is ignored
while
E
is “L”.
When the BYTE pin level is “H”, port P2 functions as an address
output pin while
E
is “H” and as an even and odd address data I/O pin
while
E
is “L”. However, if an internal memory is read, external data is
ignored while
E
is “L”.
Ports P3
0
, P3
1
, P3
2
, and P3
3
become R/
W
,
BHE
, ALE, and
HLDA
output pin respectively and lose their I/O port functions.
R/
W
is a read/write signal which indicates a read when it is “H” and a
___
BHE
is a byte high enable signal which indicates that an odd address
is accessed when it is “L”.
Therefore, two bytes at even and odd addresses are accessed
simultaneously when address A
0
is “L” and
BHE
is “L”.
ALE is an address latch enable signal used to latch the address signal
from a multiplexed signal of address and data. The latch is transparent
while ALE is “H” to let the address signal pass through and held
____
HLDA
is a hold acknowledge signal and is used to notify externally
when the microcomputer receives
HOLD
Ports P4
0
and P4
1
become
HOLD
and
RDY
input pin, respectively,
____
HOLD
is a hold request signal. It is an input signal used to put the
microcomputer in hold state.
HOLD
input is accepted when the internal
clock
falls from “H” level to “L” level while the bus is not used.
Ports P0, P1, P2, P3
0
and P3
1
are floating while the microcomputer
stays in hold state. These ports become floating after one cycle of
internal clock
later than
HLDA
signal changes to “L” level. At
releasing hold state, these ports are released from floating state after
one cycle of internal clock
later than
HLDA
signal changes to “H”
___
RDY
is a ready signal. When this signal goes “L”, the internal clock
stops at “L”.
RDY
is used when a slow external memory is attached.
Port P4
2
becomes a normal I/O port when bit 7 of the processor
mode register 0 is “0” and becomes an output pin for clock
bit 7 is “1”. The
even when internal clock
stops because of “L” input to the
RDY
pin.
_
___
____
___
1
when
1
output is independent of
RDY
and does not stop
External bus mode B
E
/
RDE
becomes the output pin for
RDE
.
___
RDE
is a read-enable signal and is “L” during the data read term in
the read cycle. When the internal memory area is read,
RDE
can be
fixed to “H” by setting the signal output disabe selection bit (bit 6 of
the oscillation circuit control register) to “1”.
Ports P0
6
and P0
7
become the output pins for addresses A
16
A
17
, respectively. Similarly, port P0
5
becomes the output pin for
RSMP
,
and ports P0
0
to P0
4
become the output pins for
CS
0
to
CS
4
,
___
___
CS
0
to
CS
4
are the chip select signals and are “L” when the address
shown in Table 8 is accessed.
RSMP
is the ready-sampling signal
which is output for the
RDY
input described later when the external
memory area is accessed. By inputting logical AND of
RSMP
and
___
____
___
CS
n
(n = 0 to 4) to the
RDY
pin, read/write term for any address areas
can be extended by 1 cycle of clock
term can also be extended by 2 cycles of clock
function and wait 0/1 function specified with the wait bit are used
together.
Port P1 has two functions depending on the level of the BYTE pin.
In bose cases, the I/O port function is lost.
When the BYTE pin level is “L”, port P1 functions as an address (A
15
to A
8
) output pin while
RDE
WEL
,
WEH
are “H” and as an odd
___
address data I/O pin while
RDE
or
WEL
,
WEH
are “L”. However, if an
internal memory is read, external data is ignored while
RDE
is “L”.
When the BYTE pin level is “H”, port P1 functions as an address
output pin.
Port P2 has two functions depending on the level of the BYTE pin.
In bose cases, the I/O port function is lost.
When the BYTE pin level is “L”, port P2 functions as an address (A
0
to A
7
) output pin while
RDE
WEL
,
WEH
are “H” and as an even
___
address data I/O pin while
RDE
or
WEL
,
WEH
are “L”. However, if an
internal memory is read, external data is ignored while
RDE
is “L”.
When the BYTE pin level is “H”, port P2 functions as an address (A
0
to A
7
) output pin while
RDE
or
WEL
,
WEH
odd address data I/O pin while
RDE
or
WEL
WEH
are “L”. However, if
an internal memory is read, external data is ignored while
RDE
is “L”.
Ports P3
0
, P3
1
, P3
2
, and P3
3
become
WEL
,
WEH
, ALE, and
HLDA
___ ___
WEL
WEH
are the write-enable low signal and the write-enable high
signal, respectively. These signals go “L” during the data write term
of the write cycle, but their operations differ depending on the BYTE
pin level.
In the case the BYTE pin level is “L”,
WEL
is “L” when writing to
an even address,
WEH
is “L” when writing to an odd address, and
both
WEL
and
WEH
are “L” when writing to even and odd addresses.
___
___
___
WEL
is “L”, and
WEH
retains “H”.
WEL
and
WEH
can also be fixed to
“H” when the internal memory is accessed, same as
RDE
, by writing
“1” to the signal output disable selection bit.
ALE is an address latch enable signal used to latch the address signal
from a multiplexed signal of address and data. The latch is transparent
while ALE is “H” to let the address signal pass through and held
____
HLDA
is a hold acknowledge signal and is used to notify externally
when the microcomputer receives
HOLD
input and enters into hole
state.
____
Ports P4
0
and P4
1
become
HOLD
and
RDY
input pin, respectively,
____
HOLD
is a hold request signal. It is an input signal used to put the
microcomputer in hold state.
HOLD
input is accepted when the internal
clock
falls from “H” level to “L” level while the bus is not used.
Ports P0, P1, P2, P3
0
, P3
1
, and pin
E
/
RDE
are floating while the
microcomputer stays in hold state. These ports become floating after
one cycle of internal clock
later than
HLDA
signal changes to “L”
level. At releasing hold state, these ports are released from floating
state after one cycle of internal clock
___
RDY
is a ready signal. If this signal goes “L”, the internal clock
stops at “L”.
RDY
is used when slow external memory is attached.
Port P4
2
becomes a normal I/O port when bit 7 of the processor
___
1
. In addition, the read/write
1
if the above
___ ___
___
___
___
later than
HLDA
signal
相關(guān)PDF資料
PDF描述
M37736EHB PROM VERSION OF M37736EHBXXXGP
M37736EHL PROM VERSION OF M37736MHLXXXHP(MICROCOMPUTERS)
M37736EHBGS PROM VERSION OF M37736EHBXXXGP
M37736EHLXXXHP PROM VERSION OF M37736MHLXXXHP(MICROCOMPUTERS)
M37736MHLXXXHP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M37736MHBXXXGP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M37736MHL 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M37736MHLXXXHP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M37753FFCFP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE CHIP 16 BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
M37753FFCHP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE CHIP 16 BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*