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參數(shù)資料
| 型號： | M37736EHBXXXGP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | PROM VERSION OF M37736MHBXXXGP(MICROCOMPUTERS) |
| 中文描述： | PROM的版本M37736MHBXXXGP（微型） |
| 文件頁數(shù)： | 30/96頁 |
| 文件大?。?/td> | 1328K |
| 代理商： | M37736EHBXXXGP |
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PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
30
SERIAL I/O PORTS
Three independent serial I/O ports are provided.
Figure 36 shows a block diagram of the serial I/O ports.
Table 5 shows the functional differences of three serial I/O ports
(UART 0, 1, 2).
Bits 0, 1, and 2 of the UARTi (i = 0, 1, 2) transmit/receive mode
register shown in Figure 37 are used to determine whether to use
port P8 or port P10 as a parallel port, a clock synchronous serial I/O
port, or an asynchronous serial I/O port (UART) using start and stop
bits.
Fig. 36 Serial I/O port block diagram
Fig. 37 UARTi transmit/receive mode register bit configuration
UART 0 transmit/receive mode register 30
16
UART 1 transmit/receive mode register 38
16
Serial I/O mode selection bits
0 0 0 : Parallel port
0 0 1 : Clock synchronous
1 0 0 : 7-bit UART
1 0 1 : 8-bit UART
1 1 0 : 9-bit UART
Internal clock/External clock selection bit
0 : Internal clock
1 : External clock
Stop bit length selection bit
0 : 1 stop bit
1 : 2 stop bits
Odd/even parity selection bit
0 : Odd parity
1 : Even parity
Parity enable bit
0 : No parity
1 : With parity
Sleep function selection bit
0 : No sleep
1 : Sleep
Addresses
7
6
5 4
3
2 1
0
Data bus (odd)
Data bus (even)
Bit converter
0
0
0
0
0
0
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
Receive register
Receive
buffer register
UART0 (Addresses 37
16
, 36
16
)
UART1 (Addresses 3F
16
, 3E
16
)
UART2 (Addresses 6B
16
, 6A
16
)
Reccircuit
RxDi
Data bus (even)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
Transmisson register
UART0 (Addresses 33
16
, 32
16
)
UART1 (Addresses 3B
16
, 3A
16
)
UART2 (Addresses 67
16
, 66
16
)
Bit converter
(Note)
control circuit
Transmission
buffer register
revePolarity
f
2
f
16
f
64
f
512
CLKi
CTSi/RTSi
1/16 Divider
UART receive
Clock synchronous
UART transmission
1/16 Divider
Clock synchronous
Clock synchronous
(Internal clock)
1/2 Divider
Clock synchronous
(External clock)
1/(n + 1)
Divider
External
Internal
Clock source selection
Bit rate
generator
UART0
(Address 31
16
)
UART1
(Address 39
16
)
UART2
(Address 65
16
)
Receive clock
Transmission clock
Data bus (odd)
TxDi
Clock synchronous
(Internal clock)
(Note)
(Note)
(Note)
Note.
UART2 does not include the bit converter, the polarity
reversing circuit and the
RTS
i
output.
UART 2 transmit/receive mode register 64
16
Address
Serial I/O mode selection bits
0 0 1 : Clock synchronous
1 0 0 : 7-bit UART
1 0 1 : 8-bit UART
1 1 0 : 9-bit UART
Internal clock/External clock selection bit
0 : Internal clock
1 : External clock
Stop bit length selection bit
0 : 1 stop bit
1 : 2 stop bits
Odd/even parity selection bit
0 : Odd parity
1 : Even parity
Parity enable bit
0 : No parity
1 : With parity
6 5
4
3 2
1
0
The switch of A-D conversion interrupt and UART2 transmit/receive
interrupt is performed by bits 0 to 2. When selecting a parallel port, A-D
conversion interrupt is valid. When selecting a clock synchronous serial
I/O port or a UART, UART2 transmit/receive interrupt is valid.
Note.
7
(Note)
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