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參數(shù)資料
| 型號： | M37542M4-XXXSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | 0.400 INCH, PLASTIC, SDIP-32 |
| 文件頁數(shù)： | 22/68頁 |
| 文件大?。?/td> | 1191K |
| 代理商： | M37542M4-XXXSP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7542 Group
MITSUBISHI MICROCOMPUTERS
29
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
qTimer A,B
Timer A and Timer B are 16-bit timers and counts the signal which
is the oscillation frequency selected by setting of the timer count
source set register (TCSS). Timer A and Timer B have the same
function except of the count source clock selection.
The count source clock of Timer A is selected from among 1/2,1/
16, 1/32, 1/64, 1/128, 1/256 of f(XIN) clock and ring oscillator
clock.
The count source clock of Timer B is selected from among 1/2, 1/
16, 1/32, 1/64, 1/128, 1/256 of f(XIN) clock and Timer A underflow.
Timer A (B) consists of the low-order of Timer A: TAL (Timer B:
TBL) and the high-order of Timer A: TAH (Timer B: TBH). Timer A
(B) is decremented by 1 when each time of the count clock is in-
put. When the contents of Timer A (B) reach “000016”, an
underflow occurs at the next count clock, and the timer latch is re-
loaded into timer. When Timer A (B) underflows, the Timer A (B)
interrupt request bit is set to “1”.
Timer A (B) has the Timer A (B) latch to retain the load value. The
value of timer A (B) latch is set to Timer A (B) at the timing of Timer
A (B) underflow. The division ratio of Timer A (B) is 1/(n+1) pro-
vided that the value of Timer A (B) is n.
When writing to both the low-order of Timer A (B) and the high or-
der of Timer A (B) is executed, writing to “l(fā)atch only” or “l(fā)atch and
timer” can be selected by the setting value of the timer A (B) write
control bit.
When reading from Timer A (B) register is executed, the count
value of Timer A (B) is read out.
Be sure to write to/read out the low-order of Timer A (B) and the
high-order of Timer A (B) in the following order;
Read
Read the high-order of Timer A (B) first, and the low-order of Timer
A (B) next and be sure to read both high-order and low-order.
Write
Write to the low-order of Timer A (B) first, and the high-order of
Timer A (B) next and be sure to write both low-order and high or-
der.
Timer A and Timer B can be used for the timing timer of Input cap-
ture and Output compare function.
s Notes on Timer A, B
(1) Setting of timer value
When “1: Write to only latch” is set to the timer A (B) write control
bit, written data to timer register is set to only latch even if timer is
stopped. Accordingly, in order to set the initial value for timer when
it is stopped, set “0: Write to latch and timer simultaneously” to
timer A (B) write control bit.
(2) Read/write of timer A
Stop timer A to read/write its data when the system is in the follow-
ing state;
CPU operation clock source: XIN oscillation
Timer A count source: Ring oscillator output
(3) Read/write of timer B
Stop timer B to read/write its data when the system is in the fol-
lowing state;
CPU operation clock source: XIN oscillation
Timer B count source: Timer A underflow
Timer A count source: Ring oscillator output
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