參數(shù)資料
型號(hào)： M37542F8VGP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PQFP32
封裝： 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁(yè)數(shù)： 20/68頁(yè)
文件大?。?/td> 1191K
代理商： M37542F8VGP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7542 Group
MITSUBISHI MICROCOMPUTERS
27
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
(4) Pulse width measurement mode
In the pulse width measurement mode, the pulse width of the sig-
nal input to P14/CNTR0 pin is measured.
The operation of Timer X can be controlled by the level of the sig-
nal input from the CNTR0 pin.
When the CNTR0 active edge switch bit is “0”, the signal selected
by the timer X count source selection bit is counted while the input
signal level of CNTR0 pin is “H”. The count is stopped while the
pin is “L”. Also, when the CNTR0 active edge switch bit is “1”, the
signal selected by the timer X count source selection bit is
counted while the input signal level of CNTR0 pin is “L”. The count
is stopped while the pin is “H”.
Timer X can stop counting by setting “1” to the timer X count stop
bit in any mode.
Also, when Timer X underflows, the timer X interrupt request bit is
set to “1”.
Note on Timer X is described below;
s Note on Timer X
(1) CNTR0 interrupt active edge selection-1
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR0 interrupt request bit is set to “1” at the rising edge of
CNTR0 pin input signal.
(2) CNTR0 interrupt active edge selection-2
According to the setting value of CNTR0 active edge switch bit,
the interrupt request bit may be set to “1”.
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding interrupt enable bit to “0” (disabled).
Set the active edge switch bit.
Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Set the corresponding interrupt enable bit to “1” (enabled).
Fig. 24 Structure of timer X mode register
Fig. 25 Timer count source set register
Timer X mode register
(TXM : address 002B16, initial value: 0016)
CNTR0 active edge switch bit
0 : Interrupt at falling edge
Count at rising edge
(in event counter mode)
1 : Interrupt at rising edge
Count at falling edge
(in event counter mode)
Timer X operating mode bits
b1 b0
0
0 : Timer mode
0
1 : Pulse output mode
1
0 : Event counter mode
1
1 : Pulse width measurement mode
Not used (return “0” when read)
Timer X count stop bit
0 : Count start
1 : Count stop
b7
b0
P03/TXOUT output valid bit
0 : Output invalid (I/O port)
1 : Output valid (Inverted CNTR0 output)
b7
b0
Timer X count source selection bits
b1 b0
0
0 : f(XIN)/16
0
1 : f(XIN)/2
1
0 : f(XIN) (Note 1)
1
1 : Not available
Timer A count source selection bits
b4 b3 b2
000 : f(XIN)/16
001 : f(XIN)/2
010 : f(XIN)/32
011 : f(XIN)/64
100 : f(XIN)/128
101 : f(XIN)/256
110 : Ring oscillator output (Note 2)
111 : Not available
Timer B count source selection bits
b7 b6 b5
000 : f(XIN)/16
001 : f(XIN)/2
010 : f(XIN)/32
011 : f(XIN)/64
100 : f(XIN)/128
101 : f(XIN)/256
110 : Timer A underflow
111 : Not available
Notes 1: f(XIN) can be used as timer X count source when using
a ceramic resonator or ring oscillator.
Do not use it at RC oscillation.
2: Ring oscillator can be used when the ring oscillator is enabled by bit 3 of CPUM.
Timer count source set register
(TCSS : address 002A16, initial value: 0016)
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