參數(shù)資料
型號(hào)： M37542F8VGP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 4 MHz, MICROCONTROLLER, PQFP32
封裝： 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁(yè)數(shù)： 10/68頁(yè)
文件大?。?/td> 1191K
代理商： M37542F8VGP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7542 Group
MITSUBISHI MICROCOMPUTERS
18
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
Fig. 18 Block diagram of ports (1)
(1) Port P00
Direction
register
Data bus
Port latch
Pull-up control
To key input interrupt
generating circuit
Capture 0 input
P00 key-on wakeup
selection bit
Drive capacity
control
Capture 0 input control
(2) Ports P01, P02
Compare output
Direction
register
Data bus
Port latch
Pull-up control
To key input interrupt
generating circuit
Compare output control
Drive capacity
control
(3) Port P03
Timer output
Direction
register
Data bus
Port latch
Pull-up control
To key input interrupt
generating circuit
P03/TXOUT output valid
Drive capacity
control
(4) Port P04
Serial I/O2 input
Direction
register
Data bus
Port latch
Pull-up control
To key input interrupt
generating circuit
Serial I/O2 enable bit
Drive capacity
control
P04 key-on wakeup
selection bit
Receive enable bit
(5) Port P05
Serial I/O2 output
Direction
register
Data bus
Port latch
Pull-up control
To key input interrupt
generating circuit
Serial I/O2 enable bit
Drive capacity
control
Transmit enable bit
P05/TxD2 P-channel output
disable bit
(6) Port P06
Serial I/O2 clock output
Direction
register
Data bus
Port latch
Pull-up control
To key input interrupt
generating circuit
Serial I/O2 mode selection bit
Drive capacity
control
Serial I/O2 enable bit
Serial I/O2 synchronous
clock selection bit
Serial I/O2 clock input
P06 key-on wakeup
selection bit
Serial I/O2 enable bit
(7) Port P07
Serial I/O2 ready output
Direction
register
Data bus
Port latch
Pull-up control
To key input interrupt
generating circuit
Serial I/O2 mode selection bit
Serial I/O2 enable bit
SRDY2 output enable bit
Drive capacity
control
相關(guān)PDF資料
PDF描述
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