參數(shù)資料
型號: M37534E4GP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PQFP32
封裝: 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁數(shù): 24/53頁
文件大?。?/td> 680K
代理商: M37534E4GP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7534 Group
MITSUBISHI MICROCOMPUTERS
30
qSerial I/O2
The serial I/O2 function can be used only for clock synchronous se-
rial I/O.
For clock synchronous serial I/O2 the transmitter and the receiver
must use the same clock. When the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
[Serial I/O2 control register] SIO2CON
The serial I/O2 control register contains 8 bits which control various
serial I/O functions.
For receiving, set “0” to bit 3.
When receiving, bit 7 is cleared by writing dummy data to serial I/
O2 register after shift is completed.
Bit 7 is set earlier a half cycle of shift clock than completion of shift
operation. Accordingly, when checking shift completion by using
this bit, the setting is as follows:
(1) check that this bit is set to “1”,
(2) wait a half cycle of shift clock,
(3) read/write to serial I/O2 register.
Fig. 32 Structure of serial I/O2 control registers
Fig. 33 Block diagram of serial I/O2
Serial I/O2 control register
(SIO2CON: address 003016)
SDATA pin selection bit (Note)
0 : I/O port/SDATA input
1 : SDATA output
Internal synchronous clock selection bits
000 : f(XIN)/8
001 : f(XIN)/16
010 : f(XIN)/32
011 : f(XIN)/64
110 : f(XIN)/128
111 : f(XIN)/256
b7
b0
Not used
(returns “0” when read)
Transfer direction selection bit
0 : LSB first
1 : MSB first
SCLK pin selection bit
0 : External clock (SCLK is an input)
1 : Internal clock (SCLK is an output)
Transmit / receive shift completion flag
0 : shift in progress
1 : shift completed
Note : When using it as an SDATA input, set the port P13
direction register to “0”.
“1”
“0”
“1”
“0”
“1”
1/8
1/16
1/32
1/64
1/128
1/256
XIN
Data bus
Serial I/O2
interrupt request
SDATA pin selection bit
Serial I/O counter 2 (3)
Serial I/O shift register 2 (8)
SCLK pin selection bit
Internal synchronous
clock selection bits
Divider
P12/SCLK
P13/SDATA
P12 latch
SCLK pin
selection bit
SCLK
P13 latch
SDATA pin selection bit
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