參數(shù)資料
型號： M37532E8FP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO36
封裝： 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-36
文件頁數(shù)： 11/51頁
文件大?。?/td> 736K
代理商： M37532E8FP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7532 Group
MITSUBISHI MICROCOMPUTERS
18
Timers
The 7532 Group has 3 timers: timer X, timer 1 and timer 2.
The division ratio of every timer and prescaler is 1/(n+1) provided
that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches “0”, an
underflow occurs at the next count pulse, and the corresponding timer
latch is reloaded into the timer. When a timer underflows, the inter-
rupt request bit corresponding to each timer is set to “1”.
qTimer 1, Timer 2
Prescaler 12 always counts f(XIN)/16. Timer 1 and timer 2 always
count the prescaler output and periodically sets the interrupt request
bit.
qTimer X
Timer X can be selected in one of 4 operating modes by setting the
timer X mode register.
Timer Mode
The timer counts the signal selected by the timer X count source
selection bit.
Pulse Output Mode
The timer counts the signal selected by the timer X count source
selection bit, and outputs a signal whose polarity is inverted each
time the timer value reaches “0”, from the CNTR0 pin.
When the CNTR0 active edge switch bit is “0”, the output of the
CNTR0 pin is started with an “H” output.
At “1”, this output is started with an “L” output. When using a timer in
this mode, set the port P14 direction register to output mode.
Event Counter Mode
The operation in the event counter mode is the same as that in the
timer mode except that the timer counts the input signal from the
CNTR0 pin.
When the CNTR0 active edge switch bit is “0”, the timer counts
the rising edge of the CNTR0 pin. When this bit is “1”, the timer
counts the falling edge of the CNTR0 pin.
Pulse Width Measurement Mode
When the CNTR0 active edge switch bit is “0”, the timer counts the
signal selected by the timer X count source selection bit while the
CNTR0 pin is “H”. When this bit is “1”, the timer counts the signal
while the CNTR0 pin is “L”.
In any mode, the timer count can be stopped by setting the timer X
count stop bit to “1”. Each time the timer overflows, the interrupt
request bit is set.
Fig. 18 Structure of timer X mode register
Fig. 19 Timer count source set register
Timer X mode register
(TM : Address 002B16)
CNTR0 active edge switch bit
0 : Interrupt at falling edge
Count at rising edge
(in event counter mode)
1 : Interrupt at rising edge
Count at falling edge
(in event counter mode)
Timer X operating mode bits
b1 b0
0
0 : Timer mode
0
1 : Pulse output mode
1
0 : Event counter mode
1
1 : Pulse width measurement mode
Not used (return “0” when read)
Timer X count stop bit
0 : Count start
1 : Count stop
b7
b0
Timer count source set register
(TCSS : Address 002E 16)
b7
b0
Timer X count source selection bit (Note)
0 : f(XIN)/16
1 : f(XIN)/2
Not used (return “0” when read)
Note : To switch the timer X count source selection bit ,
stop the timer X count operation.
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