參數資料
型號： M3727GM8-XXXSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42
文件頁數： 2/129頁
文件大小： 1357K
代理商： M3727GM8-XXXSP
M3727GM6/M8–XXXSP/FP M37272E8SP/FP
Rev.1.00
Apr 01, 2001
page 10 of 127
REJ03B0132-0100Z
Fig. 7.2 I/O Pin Block Diagram (2)
Internal circuit
P52–P55
P50, P51
Internal circuit
CMOS input
Ports P50, P51
Note : Each pin is also used
as follows :
P50 : HSYNC
P51 : VSYNC
CMOS output
Ports P52–P55
Note : Each pin is also used
as follows :
P52 : R
P53 : G
P54 : B
P55 : OUT1
CMOS output
Ports P1, P2, P30, P31
Notes 1: Each port is also used as follows :
P10 : OUT2
P11 : SCL1
P12 : SCL2
P13 : SDA15
P14 : SDA2
P15 : AD1/INT3
P16 : AD2
P17 : AD3
2: The output structure of ports P30 and P31 can be selected either CMOS output or N-channel open-
drain output structure (when selecting N-channel open-drain, it is the same with P00–P07).
3: The output structure of ports P11–P14 is N-channel open-drain output when using as multi-master
I2C-BUS interface (when selecting N-channel open-drain, it is the same with P00–P07).
4: The output structure of ports P20 and P21 is N-channel open-drain output when using as serial
output (when selecting N-channel open-drain, it is the same with P00–P07).
P20 : SCLK
P21 : SOUT
P22 : SIN
P23 : TIM3
P24 : TIM2
P30 : AD5
P31 : AD6
Ports P1, P2, P30, P31
Direction register
Port latch
Data bus
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