參數(shù)資料
型號： M3727GM8-XXXSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42
文件頁數(shù)： 116/129頁
文件大?。?/td> 1357K
代理商： M3727GM8-XXXSP
M3727GM6/M8–XXXSP/FP M37272E8SP/FP
Rev.1.00
Apr 01, 2001
page 87 of 127
REJ03B0132-0100Z
8.11.13 OSD Output Pin Control
The OSD output pins R, G, B and OUT1 can also function as ports
P52–P55. Set corresponding bit of the OSD port control register (ad-
dress 00CB16) to “0” to specify these pins as OSD output pins, or set
it to “1” to specify it as a general-purpose port P5.
The OUT2 can also function as port P10. Set bit 0 of the port P1
direction register (address 00C316) to “1” (output mode). After that,
set bit 7 of the OSD port control register to “1” to specify the pin as
OSD output pin, or set it to “0” to specify as port P10.
The input polarity of the HSYNC, VSYNC and output polarity of signals
R, G, B, OUT1 and OUT2 can be specified with the I/O polarity con-
trol register (address 00D8) . Set a bit to “0” to specify positive polar-
ity; set it to “1” to specify negative polarity (refer to Figure 8.11.13).
The structure of the OSD port control register is shown in Figure
8.11.28.
Fig. 8.11.28 OSD Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
OSD port control register (PF) [Address 00CB16]
B
Name
Functions
After reset
R W
OSD Port Control Register
0
2
0
30 : G signal output
1 : Port P53 output
0
Fix these bits to 0.
R
R W
0, 1
Port P53 output signal
selection bit (PF3)
4
0 : B signal output
1 : Port P54 output
0
R W
Port P54 output signal
selection bit (PF4)
0R W
0 : R signal output
1 : Port P52 output
Port P52 output signal
selection bit (PF2)
5
0 : OUT1 signal output
1 : Port P53 output
Port P55 output signal
selection bit (PF5)
70 : Port P10 output
1 : OUT2 signal output
Port P10 output signal
selection bit (PF7)
0
Nothing is assigned. This bit is write disable bit.
When this bit is read out, the value is 0.
R
6
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