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參數(shù)資料
| 型號： | M37274EFSP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | CONN HEADER 14POS SGL PCB 30GOLD |
| 中文描述： | 單芯片8位CMOS微機(jī)隱蔽字幕解碼器和屏幕顯示控制器 |
| 文件頁數(shù)： | 52/147頁 |
| 文件大?。?/td> | 2042K |
| 代理商： | M37274EFSP |
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52
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Function
In conformity with Philips I
2
C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I
2
C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at
φ
= 4 MHz)
Table 7. Multi-master I
2
C-BUS Interface Functions
Item
Format
Communication mode
SCL clock frequency
φ
: System clock = f(X
IN
)/2
Note:
We are not responsible for any third party’s infringement of
patent rights or other rights attributable to the use of the con-
trol function (bits 6 and 7 of the I
2
C control register at address
00F9
16
) for connections between the I
2
C-BUS interface and
ports (SCL1, SCL2, SDA1, SDA2).
MULTI-MASTER I
2
C-BUS INTERFACE
The multi-master I
2
C-BUS interface is a serial communications cir-
cuit, conforming to the Philips I
2
C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchronous
functions, is useful for the multi-master serial communications.
Figure 50 shows a block diagram of the multi-master I
2
C-BUS inter-
face and Table 7 shows multi-master I
2
C-BUS interface functions.
This multi-master I
2
C-BUS interface consists of the I
2
C address reg-
ister, the I
2
C data shift register, the I
2
C clock control register, the I
2
C
control register, the I
2
C status register and other control circuits.
Fig. 50. Block Diagram of Multi-master I
2
C-BUS Interface
I
2
C address register (S0D)
b7
b0
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1SAD0 RBW
Noise
elimination
circuit
Serial
data
(SDA)
Address comparator
b7
I C data shift register
b0
Data
control
circuit
I
2
C clock control register (S2)
System clock
( )
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
b7
MST TRX BB
PIN
AL AAS AD0 LRB
b0
I C status
register
(S1)
b7
b0
BSEL1
BSEL0
10BIT
SAD
ALS
BC2 BC1 BC0
I
2
C clock control register (S1D)
Bit counter
BB
circuit
Clock
control
circuit
Noise
elimination
circuit
Serial
clock
(SCL)
b7
ACKBIT
b0
FAST
Internal data bus
Clock division
S0
AL
circuit
ESO
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