參數(shù)資料
型號： M37274EFSP
廠商： Mitsubishi Electric Corporation
英文描述： CONN HEADER 14POS SGL PCB 30GOLD
中文描述： 單芯片8位CMOS微機隱蔽字幕解碼器和屏幕顯示控制器
文件頁數(shù)： 144/147頁
文件大?。?/td> 2042K
代理商： M37274EFSP
144
MITSUBISHI MICROCOMPUTERS
M37274EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Vertical Position Register 2i
Window L Register 2
Address 021F
16
Addresses 0230
16
to 023B
16
Vertical Position Register 1i
Addresses 0220
16
to 022B
16
b7b6b5b4b3b2b1b0
Vertical position register 1i (VP1i) (i = 1 to 16) [Addresses 0220
16
to 022F
16
]
B
0
to
7
Name
Functions
After reset
Indeterminate
R W
R W
Vertical Position Register 1i
Control bits of vertical
display start positions
(VP1i0 to VP1i7)
(See note 1)
Vertical display start positions
(low-order 8 bits)
T
H
(setting value of low-order 2 bits of VP2i
16
2
+ setting value of low-order 4 bits of VP1i
16
1
+ setting value of low-order 4 bits of VP1i
16
0
)
Notes 1:
Set values except “00
16
” “01
16
” to VP1i when VP2i is “00
16
.”
2:
T
H
is cycle of H
SYNC
.
b7b6b5b4b3b2b1b0
Vertical position register 2i (VP2i) (i = 1 to 16) [Addresses 0230
16
to 023F
16
]
B
Name
Functions
After reset
Indeterminate
R W
R W
Vertical Position Register 2i
0, 1 Control bits of vertical
display start positions
(VP1i0, VP1i1)
(See note 1)
Vertical display start positions
(high-order 2 bits)
T
H
(setting value of low-order 2 bits of VP2i
16
2
+ setting value of low-order 4 bits of VP1i
16
1
+ setting value of low-order 4 bits of VP1i
16
0
)
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are indeterminate.
2
to
7
Indeterminate
R —
Notes 1:
Set values except “00
16
” “01
16
” to VP1i when VP2i is “00
16
.”
2:
T
H
is cycle of H
SYNC
.
b7b6b5b4b3b2b1b0
Window L register 2 (WL2) [Address 021F
16
]
B
Name
Functions
After reset
Indeterminate
R W
R W
Window L Register 2
0, 1 Control bits of window
top boundary
(WL20, WL21)
(See note 1)
Top boundary position (high-order 2 bits)
T
H
(setting value of low-order 2 bits of WL2
16
2
+ setting value of high-order 4 bits of WL1
16
1
+ setting value of low-order 4 bits of WL1
16
0
)
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are indeterminate.
2
to
7
Indeterminate
R —
Notes 1:
Set values fit for the following condition: (WH1+WH2
16
2
)<(WL1+WL2
16
2
)
2:
T
H
is cycle of H
SYNC
.
3:
WL1: Window L register 1
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